Fully Depleted Silicon on Insulator devices
Brian Bailey, EETimes
6/19/2012 11:37 AM EDT
For decades, we rode the technology wave by building smaller and smaller transistors into a bulk silicon wafer. Around 90nm, we began to realize that there were problems ahead as voltage scaling slowed and leakage currents increased. Small changes were made in the process to lengthen the bulk lifetime, but there are reasons to look at completely different ways to build circuitry, especially at the latest geometries of 28 and 20 nm. Once such possible way forward is Fully Depleted Silicon of Insulator (FD SOI). Researchers believe that this technology will scale down to 11nm.
FD SOI relies on an ultra-thin layer of silicon over a Buried Oxide layer. Transistors built into this top silicon layer are Ultra-Thin body devices and have unique, extremely attractive characteristics according to Soitec, a manufacturer of the wafers needed to build these products. I spoke to Soitec’s Steve Longoria – SVP Business Development, who walked me through some aspects of the technology.
Related Semiconductor IP
- RISC-V CPU IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
Related White Papers
- Fully depleted silicon technology to underlie energy-efficient designs at 28 nm and beyond
- The Internet of Cars Is Paved With Silicon
- Reconfiguring Design -> Adaptive computing makes efficient use of silicon
- Retargeting IP -> Silicon prototyping verifies IP functions
Latest White Papers
- New Realities Demand a New Approach to System Verification and Validation
- How silicon and circuit optimizations help FPGAs offer lower size, power and cost in video bridging applications
- Sustainable Hardware Specialization
- PCIe IP With Enhanced Security For The Automotive Market
- Top 5 Reasons why CPU is the Best Processor for AI Inference