Increasing bandwidth in industrial applications with FPGA co-processors

By Michael Parker, Altera Corp.
pldesignline.com (February 01, 2010)

FPGAs have long been used as primary and co-processors in telecommunications. Digital signal processing (DSP) in industrial applications often has fundamental differences from the typical telecommunication application. In telecommunications, the input data is commonly high data rates with real time processing constraints requiring completion of calculations between successive input data buffers or samples. With a DSP processor, this may allow for only a few tens of instructions per input data sample. This instruction bandwidth limitation can be minimized by taking advantage of the multiple processing units in some DSP processors. However, creating the specialized pipe-lined code to take true advantage of this parallelism requires hand optimization of assembly language routines. Maintenance, re-usability, and implementation of this type of code can be troublesome and expensive at best. Additionally, the degree of parallelism (simultaneous executions) is relatively low, and may still not permit the real time processing constraints to be met.

A better alternative for high-bandwidth computations is to use an FPGA as a co-processor that integrates the repetitive, speed-critical portions of an algorithm into the FPGA. With an FPGA and automated design software, design engineers have the ability to optimize system performance in ways not possible with a traditional DSP. This article discusses the general issues of moving part, or all, of a DSP industrial application onto an FPGA using system software design tools.

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