Importance of Dynamic Programming for Achieving Hard Breakdown in Anti-Fuse Technology

By SST

Abstract

As System-on-chip (SOC) developers continue to look for ways to reduce costs and time to market, considering the different non-volatile memory (NVM) options to add flexibility to their products is important. Over the last few years, the NVM market has been flooded with new solutions. Now, having customers weigh the benefits of reliability, options, and costs during project development is even more critical. With antifuse vendors targeting a wider range of functionality and products, noting the reliability concerns of reaching hard breakdown (HBD) compared to soft breakdown (SBD) is vital.

Background on Antifuse OTP

Antifuse technology functions by a mechanism that is the opposite of fuse technology. When a fuse is programmed, the conduction path is destroyed, resulting in high resistance and a low resistance when not programmed.

In an antifuse device, the circuit begins in a high resistance state, and when programmed, maintains a low resistance state. The resistance change is achieved by applying a high voltage to the programming gate. Hard breakdown occurs after several stages of programming.

1.   Normal gate with no stress. Only natural defects are present and based on proximity, gate leakage can occur.
2.   Stress Induced Leakage can induce a possible situation where Soft breakdown can occur. The dotted circle can either remain, leading to Soft breakdown, or dissipate and revert back to a normal gate.
3.   Soft Breakdown has occurred and a small filament made up of trapped charges has formed. This stage paves the way to Hard Breakdown but is NOT a permanent change.
4.   Hard Breakdown has occurred due to thermal meltdown and a strong irreversible filament has been formed.

Stage 1

Defect Generation or Stress Induced Leakage Current

The first stage of oxide breakdown is oxide wear or trap charge generation. During initial programming, microscopic defects, or traps, are generated in the SiO2 layer during electric field stress. These defects lead to increased leakages across the gate. Three mechanisms can lead to this increased leakage current.

•   Direct Tunneling – Requires a fairly thin oxide for significant current
•   Fowler–Nordheim Tunneling – electrical thinning of oxide
•   Defect Generation – Charge trapping due to high electric field

All of these mechanisms lead to increased leakage currents, however, when the electrical field is removed, they return to normal operation and have limited to no change in permanent conduction.

Stage 2

Soft Breakdown (SBD) (Noise Generation)

During this stage, leakage current is significantly increased, but does not permanently damage the oxide. Unlike Hard breakdown (HBD), Soft breakdown (SBD) does not form a permanent leakage path.

Two fundamental conditions determine SBD:

•   Sudden increase in leakage current though gate oxide
•   An increase in gate signal noise.

Different phenomena can lead to the increased leakages of SBD.

Extreme trapped charge generation – When the high field is applied during programming, trapped charges begin to form conduction paths through the oxide. These paths can lead to a significant increase in leakage currents but not to Hard Breakdown.

The above figure shows how either one or multiple paths can lead to the formation of a conduction path. Although these conduction paths change the current through the device, they do not physically change the oxide for permanent conduction. The conduction changes only after the electric field is removed or over time of operation and temperature.

Oxide bumps can form at the top and bottom of the oxide also increasing leakage current but not forming a filament as pictured in Figure 2

Figure 3

Stage 3

Hard Breakdown (HBD)

Hard Breakdown is an irreversible catastrophic breakdown of an oxide. Hard Breakdown is a severe case of soft breakdown where thermal runaway has resulted in a larger conduction path. After the current path, a permanent conduction path is established from the gate to channel.

The above charts demonstrate the initial conduction difference between Hard and Soft breakdown. The chart on the left shows the progression of the breakdown event. It can be observed that when voltage is applied over a given time the current will start to increase slightly until a thermal breakdown event. The chart on the right is showing the voltage vs. current plot across the gate oxide. As the field potential across the gate is increased the current through that gate also increases until a hard breakdown event. It can be observed that the current will between soft and hard breakdown is very small compared to the tunneling current. Because of this difference, determining the point at which hard breakdown is achieved is very difficult.

Guaranteeing Hard Breakdown in Antifuse Memories

Antifuse OTP memory can be very reliable; however, certain antifuse technologies can still suffer yield problems if hard breakdown is not achieved. Since each programmed oxide is different than the next, every cell requires an individual programming time. Many antifuse

Antifuse OTP memory can be very reliable; however, certain antifuse technologies can still suffer yield problems if hard breakdown is not achieved.

There are 2 main factors that lead to a successful hard breakdown of the gate oxide, location of the breakdown event and the amount of time for the breakdown process. There have been some attempt to direct the location of the breakdown event and it is still undetermined which if any method is more or less effective. The two main methods are a split-channel device where half of the gate oxide is under thick oxide and the other half is a thin oxide. The theory is that by splitting this oxide over the gate there will be process defects and the gate oxide will be weaker at this region resulting in a set location breakdown event every time. Even though this theory could be factual there is still no guarantee that the event will not take place at another location of the gate. The other method is using a voltage gradient where the attempt is to direct the location of the breakdown event towards either the source or drain region of the device. While it is possible to improve the statistics of a breakdown event, it is still not possible to guarantee that this will lead to a source or drain region breakdown location. With both of these theories improving the statistics of the location, neither can universally lead to a set known breakdown location.

The second factor that determines a successful hard breakdown is the stress time or programming time. There are two established ways to program the antifuse device, statically or dynamically. When programming statically, a statistical average is used to set the programming time. This method can lead to bits that have not reached the hard breakdown stage or “tail bits”. The “tail bits” is a term coined by the industry to address the bits that have not reached a hard breakdown event and look as if they have reversed state or been erased. Since the location of the breakdown event cannot be guaranteed, additional programming time would be required to reach the hard breakdown conduction at the final location. So with a static timed breakdown event there will always be “tail bits” (soft breakdown) that lead to low yield for memory data retention.

In order to guarantee that hard breakdown is achieved, programming cannot be time based, but instead should be based on dynamic detection. By using dynamic detection, each bit is programmed until the hard breakdown current signature is reached. When programming with this method the breakdown location is irrelevant because the bit is being programmed until the breakdown location has formed and a hard breakdown characteristic is achieved. SST’s patented SmartBit™ has the ability to detect hard breakdown event current characteristic on a bit by bit basis. This detection technology guarantees that hard breakdown is achieved. With the implementation of the SmartBit™ cell, SST offers 100% reliability with industry leading data retention over 30 years.

Conclusion

In order to maximize reliability, sensing hard breakdown is extraordinarily advantageous. Soft breakdown closely resembles hard breakdown, but a static timed programming cannot guarantee that every bit has been programmed reliably. Hard breakdown sensing eliminates the need for added redundancy to compensate for trapped charge dissipation over extended burn-in or operation, a common problem when hard breakdown is not achieved in all bit cells.*

For more information regarding SST’s SmartBit™ OTP technology, please visit us at www.sst.com or send us an email at info@sst.com