Wind River calls reconfigurable hardware from C

Wind River calls reconfigurable hardware from C
By Chris Edwards, EE Times
May 24, 2001 (1:57 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010523S0061

LONDON — Wind River Systems Inc. (Alameda, Calif.) has revealed its approach to using programmable logic as an application accelerator for processors running its embedded operating system.

The company recently signed a deal to distribute the DK1 programmable logic tool from Celoxica Ltd. (Abingdon, England), and it has been using that arrangement to build an applications programming interface (API) and a communications protocol that a host processor and an FPGA device can use to exchange information.

"The whole concept came up from using C functions and implementing them in hardware," said Gareth Noyes, market development manager for Wind River. "We take C code and target that to the FPGA using the Celoxica software. That way, we make it look to the programmer as though the function is still running on the CPU."

The framework that Wind River and Celoxica are building consists of a driver for the OS itself and a multiplexing engine th at sits in the FPGA. The multiplexer, which works out which hardware function to call, was built using the Celoxica tools.

The driver marshals and serializes data passed by the task, making a function call to a hardware-based routine. The multiplexer takes that data and passes it to the logic that implements the function. When the return data is ready, it is passed back through the multiplexer to the driver and on up to the calling task.

To ensure real-time behavior, the OS queues in order of priority requests for FPGA processing. "It can do out-of-order function calls," Noyes said.

Tasks can make blocking or non-blocking calls. In the latter case, the OS uses a call-back function to tell the task that the data is ready.

"People are out there looking at this from a sequential point of view. This is thinking from a multitasking, real-time point of view," Noyes said.

"The key to the architecture is determining where your bottlenecks lie. We have taken a triple-DES encryption algorithm. On a PowerPC 750 running flat out, you can get 1.2 Mbits/second. On an FPGA, you can do 70 Mbits/s at only 20 MHz. That's when you start finding other bottlenecks, such as the speed of the hard disk. Over time, you can monitor the performance of the system and upgrade it."

Noyes said the C function-based approach is fundamental to the project: "It lets the CPUs and FPGAs evolve but lets the application software remain the same."

Wind River has already worked with Xilinx to define a protocol and an API, called Pave, to download configuration information to the FPGA.

According to Noyes, the current implementation puts the FPGA on the processor's memory bus, but the architecture could also handle communications over the peripheral component interface or over serial links.

Chris Edwards is the editor of Electronics Times, EE Times' sister publication in the United Kingdom.