What Are EDA's Big Three Thinking?
Messages delivered by all three CEOs to their respective users point to trouble spots, opportunities and what’s ahead for EDA.
Ed Sperling, SemiEngineering
April 24th, 2014
Over the past six weeks, the CEOs of Cadence, Synopsys and Mentor Graphics—in that order—have delivered top-down visionary messages to their user groups. Semiconductor Engineering had the opportunity to attend all three sessions, and has compiled comments from each on a variety of subjects. In some cases, all the CEOs were in sync. In others, they were not. In still others, it was difficult to tell because they approach the issues from different angles. But there were some common themes.
Related Semiconductor IP
- USB 20Gbps Device Controller
- 25MHz to 4.0GHz Fractional-N RC PLL Synthesizer on TSMC 3nm N3P
- AGILEX 7 R-Tile Gen5 NVMe Host IP
- 100G PAM4 Serdes PHY - 14nm
- Bluetooth Low Energy Subsystem IP
Related News
- Virage Logic aims to crack the Big Three
- July chip figures: What analysts are saying
- Micron-Numonyx deal: What analysts are saying
- Intel-Infineon deal: What analysts are saying
Latest News
- 2025 TSMC OIP Ecosystem Forum Highlights Aion Silicon’s Leadership in Advanced SoC Design
- Ceva Appoints Former Microsoft AI and Hardware Leader Yaron Galitzky to Accelerate Ceva’s AI Strategy and Innovation at the Smart Edge
- Dnotitia Unveils VDPU IP, the First Accelerator IP for Vector Database
- Ambient Scientific AI-native processor for edge applications offers 100x power and performance improvements over 32-bit MCUs
- Qualitas Semiconductor Signs PCIe Gen 4.0 PHY IP License Agreement with Leading Chinese Fabless Customer