What Are EDA's Big Three Thinking?
Messages delivered by all three CEOs to their respective users point to trouble spots, opportunities and what’s ahead for EDA.
Ed Sperling, SemiEngineering
April 24th, 2014
Over the past six weeks, the CEOs of Cadence, Synopsys and Mentor Graphics—in that order—have delivered top-down visionary messages to their user groups. Semiconductor Engineering had the opportunity to attend all three sessions, and has compiled comments from each on a variety of subjects. In some cases, all the CEOs were in sync. In others, they were not. In still others, it was difficult to tell because they approach the issues from different angles. But there were some common themes.
Related Semiconductor IP
- Mesochronous Bridge for PCIe/CXL
- AI-native GPU
- OpenGMSL Verification IP
- OpenGMSL Leaf IP
- FlexGen Multi-Die Smart Network-on-Chip (NoC) IP
Related News
- Virage Logic aims to crack the Big Three
- July chip figures: What analysts are saying
- Micron-Numonyx deal: What analysts are saying
- Intel-Infineon deal: What analysts are saying
Latest News
- SignatureIP Unveils MesoLink, a Mesochronous Bridge for PCIe/CXL Validation
- ICTK Partners with Jiran Security to Drive Post-Quantum Cryptography (PQC) Migration
- S2C Named Andes Technology’s 2026 Partner of the Year
- BrainChip Launches AKD1500 PCIe Card For Edge AI Evaluation Everywhere
- TDK-Micronas adopts Aniah’s AI-powered OneCheck® platform to advance automotive semiconductor development