What Are EDA's Big Three Thinking?
Messages delivered by all three CEOs to their respective users point to trouble spots, opportunities and what’s ahead for EDA.
Ed Sperling, SemiEngineering
April 24th, 2014
Over the past six weeks, the CEOs of Cadence, Synopsys and Mentor Graphics—in that order—have delivered top-down visionary messages to their user groups. Semiconductor Engineering had the opportunity to attend all three sessions, and has compiled comments from each on a variety of subjects. In some cases, all the CEOs were in sync. In others, they were not. In still others, it was difficult to tell because they approach the issues from different angles. But there were some common themes.
Related Semiconductor IP
- Multi-channel Ultra Ethernet TSS Transform Engine
- Configurable CPU tailored precisely to your needs
- Ultra high-performance low-power ADC
- HiFi iQ DSP
- CXL 4 Verification IP
Related News
- Virage Logic aims to crack the Big Three
- July chip figures: What analysts are saying
- Micron-Numonyx deal: What analysts are saying
- Intel-Infineon deal: What analysts are saying
Latest News
- proteanTecs and Gubo Technologies Collaborate to Deliver Unified Analytics Solution for Advanced Semiconductor Systems
- Cadence Completes Acquisition of Hexagon’s Design and Engineering Business, Advancing Leadership in Physical AI and Multiphysics
- TES Launches its µEngine: Parallel CPU System for Deterministic Real-Time HDL Applications
- PQShield becomes ST Authorized Partner
- sensiBel Licenses Sofics’ Advanced ESD Solutions for their Studio-quality MEMS Microphone Technology