Virage re-architects SRAM compilers for 0.18 micron

Virage re-architects SRAM compilers for 0.18 micron
By Michael Santarini, EE Times
March 29, 1999 (10:11 a.m. EST)
URL: http://www.eetimes.com/story/OEG19990329S0004

SRAM IP company Virage Logic (Fremont, Calif.) has announced the availability of its Custom-Touch application-specific embedded memory compilers for 0.18-micron process technologies and test silicon for Taiwan Semiconductor Manufacturing Co. customers.

According to Vin Ratford, vice president of marketing and sales at Virage, the company created a new architecture for its Custom-Touch 0.18-micron high-density (HD), high-speed (HS) and ultra-low-power (ULP) families that offer significant improvements in memory core power, speed, area and manufacturability over alternate compilers.

"Instead of scaling the compilers down from 0.25 to 0.18 micron, we have created new architectures for our 0.18 compilers to look at issues such as power," Ratford said. "Power management is going to be an increasingly important criterion in 0.18 micron. At a quarter micron, a lot of the emphasis was on density, with a secondary concern about power. At 0.18 mi cron, as the chips get bigger and the amount of memory gets larger, people are looking for other ways of reducing power consumption."

Ratford said Virage concentrated on reducing power for larger configurations when it was creating the new architecture for the compilers. "We wanted to do something beyond sizing the bit scales, doing the sense amplifier and clock doubling-all the things we did at 0.25 micron," Ratford said. "What we did was go one step further for 0.18 and borrowed some techniques from classical, standalone memory designs that are used to reduce power as memory scales to larger and larger sizes. We applied those techniques to our 0.18 memory compilers."

According to the company, with normal scaling from 0.25-micron to 0.18-micron process technologies, a typical single-port 32k memory design, for example, would provide a 3x reduction in power consumption. With Virage's innovative architecture, however, the HD family provides a 6x reduction in power consumption, while the ULP fa mily delivers a 16x reduction.

Ratford said that in addition to power savings, the 0.18-micron HD compiler generates memory cores that feature 2x speed improvement in cycle time and a 2x reduction in area, compared with the earlier 0.25-micron Custom-Touch HD compiler family.

The HS memory compiler targets high-performance computing and networking applications. The 0.18-compiler generates cores with cycle times 4x faster than 0.25-micron HD cores. It is also available in single- and dual-port versions and features 1,000-MHz operating frequencies for single-port, typical use and access time of less than 0.5 ns (single-port, typical), according to the company.

Ratford said that the 0.18-micron Custom-Touch family will be available in April for TSMC.

Pricing for customer-owned tooling customers (those who perform their own layout) starts at $100,000 for a one-port register file.

The company said it has teamed up with TSMC to run test silicon of the 0.18-micron memory str uctures and that data about the test structures can be reviewed by Virage and TSMC's mutual customers through a non-disclosure arrangement. Visit www.virlog.com.