Veriest Solutions and CEVA develop functional safety verification methodology for automotive devices
The methodology will be the topic of a Veriest workshop at the DVCon US 2021 conference
Petach Tikva, Israel – 17, February 2020 -- Veriest Solutions, the international Electronics Design Services house, today announced that its engineering team have collaborated with CEVA, the leading licensor of wireless connectivity and smart sensing technologies, to develop a functional safety verification methodology. The purpose of the innovative approach is to implement and verify the proper operation of safety mechanisms required in automotive and other mission-critical applications.
This method was successfully employed initially in a series of advanced DSP and AI IP cores provided by CEVA. It was subsequently also used in CEVA’s SensPro2™, a high-performance sensor hub DSP architecture for processing and fusing data from multiple sensors including camera, Radar, LiDar, Time-of-Flight, microphones and inertial measurement units.
The methodology extends the classical black-box functional verification tree with white-box error generation in a UVM environment. This ensures compliance with ISO 26262 requirements, with stricter rigor and more formalized procedures.
Ran Snir, CEVA’s Vice President of R&D said: “With the increased adoption of our cores in automotive applications, it is fundamental that we thoroughly verify the proper operation of our designs, in multiple scenarios. We have been collaborating with Veriest for many years across different projects, and we’re pleased to have jointly achieved this additional milestone”.
Moshe Zalcberg, CEO of Veriest, added: “Functional safety has become a crucial consideration for our design and verification engineering teams, with more sensing and AI functionality being deployed in vehicles. It was a privilege for Veriest to work with CEVA’s world-class technology experts to define and implement a novel approach for functional safety verification”.
This methodology will be demonstrated by Dr. Mihajlo Katona, a Sr. Verification Team Leader at Veriest, at a dedicated workshop at the DVCon US 2021 conference, taking place virtually on March,1-4.
For more details and registration: https://2021.dvcon.org/
To learn more about this collaboration with CEVA and about Safety Verification - https://bit.ly/37la7c4
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related News
- SEALSQ and IC’ALPS Join Forces to Advance Post-Quantum Secure ASICs for Automotive Functional Safety
- Arteris Ncore Cache Coherent Interconnect IP Certified for ISO 26262 Automotive Functional Safety Standard
- Arteris Celebrates 3rd Year of Automotive ISO 26262 TCL1 Functional Safety Compliance for Magillem SoC Integration Automation
- Intrinsic ID Launches First Hardware Root-of-Trust Solution to Meet Functional Safety Standards for Automotive Market
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack