Veriest Solutions and CEVA develop functional safety verification methodology for automotive devices
The methodology will be the topic of a Veriest workshop at the DVCon US 2021 conference
Petach Tikva, Israel – 17, February 2020 -- Veriest Solutions, the international Electronics Design Services house, today announced that its engineering team have collaborated with CEVA, the leading licensor of wireless connectivity and smart sensing technologies, to develop a functional safety verification methodology. The purpose of the innovative approach is to implement and verify the proper operation of safety mechanisms required in automotive and other mission-critical applications.
This method was successfully employed initially in a series of advanced DSP and AI IP cores provided by CEVA. It was subsequently also used in CEVA’s SensPro2™, a high-performance sensor hub DSP architecture for processing and fusing data from multiple sensors including camera, Radar, LiDar, Time-of-Flight, microphones and inertial measurement units.
The methodology extends the classical black-box functional verification tree with white-box error generation in a UVM environment. This ensures compliance with ISO 26262 requirements, with stricter rigor and more formalized procedures.
Ran Snir, CEVA’s Vice President of R&D said: “With the increased adoption of our cores in automotive applications, it is fundamental that we thoroughly verify the proper operation of our designs, in multiple scenarios. We have been collaborating with Veriest for many years across different projects, and we’re pleased to have jointly achieved this additional milestone”.
Moshe Zalcberg, CEO of Veriest, added: “Functional safety has become a crucial consideration for our design and verification engineering teams, with more sensing and AI functionality being deployed in vehicles. It was a privilege for Veriest to work with CEVA’s world-class technology experts to define and implement a novel approach for functional safety verification”.
This methodology will be demonstrated by Dr. Mihajlo Katona, a Sr. Verification Team Leader at Veriest, at a dedicated workshop at the DVCon US 2021 conference, taking place virtually on March,1-4.
For more details and registration: https://2021.dvcon.org/
To learn more about this collaboration with CEVA and about Safety Verification - https://bit.ly/37la7c4
Related Semiconductor IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- 1G BASE-T Ethernet Verification IP
- Network-on-Chip (NoC)
- Microsecond Channel (MSC/MSC-Plus) Controller
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
Related News
- Quintauris and IAR Join Forces to Advance Functional Safety Software for RISC-V Automotive Real-time Applications
- SEALSQ and IC’ALPS Join Forces to Advance Post-Quantum Secure ASICs for Automotive Functional Safety
- proteanTecs and Dream Chip Technologies Announce Collaboration to Advance Functional Safety in Automotive and HPC Markets
- Andes Technology Announces D23-SE: A Functional Safety RISC-V Core with DCLS and Split-Lock for ASIL-B/D Automotive Applications
Latest News
- Virtusa Acquires Bengaluru based SmartSoC Solutions, Establishing Full-Stack Service Offering from Chip to Cloud and Driving Expansion into the Semiconductor Industry
- Consumer Electronics and AI Product Launches Lift 3Q25 Top-10 Foundry Revenue by 8.1%, Says TrendForce
- Joachim Kunkel Joins Quadric Board of Directors
- RaiderChip NPU leads edge LLM benchmarks against GPUs and CPUs in academic research paper
- SEMIFIVE Secures AI Semiconductor Design Projects in Japan, Accelerating Global Expansion with New Local Subsidiary