Training firm offers free Vera TCP/IP packet generator with a built-in functional coverage tracker
EE Times: Latest News Training firm offers free verification IP | |
Richard Goering (02/26/2004 7:00 PM EST) URL: http://www.eetimes.com/showArticle.jhtml?articleID=18200879 | |
SANTA CRUZ, Calif. As a way of spreading the word about its classes and workshops, Si-Concepts is offering a free Vera TCP/IP packet generator with a built-in functional coverage tracker. The company is also offering a tutorial on coverage-driven testbenches at the DVCon conference March 1, 2004. Si-Concepts is a "design knowledge company," said Shahid Khan, president. In addition to the upcoming four-hour tutorial at DVCon, the company offers a three-day workshop, created for Synopsys, entitled "VERA II: Testbenches and Test Cases For Complex Designs." The Vera TCP/IP packet generator is available for download from Si-Concept's web site. Khan said the company is offering free verification intellectual property (IP) because they want people to register for the DVCon tutorial or the Vera II workshop. "I think people learn best looking at an example from a practical environment," he added. The packet generator produces TCP/IP packets with random payloads, and provides randomization control for header fields of a TCP/IP packet. Fields such as IP source address, IP destination address, TCP source, and destination port numbers are settable by user-specified constraints. Calculated fields such as header checksum and TCP checksum are computed correctly after randomization has occurred, Khan said. The built-in coverage tracking and reporting lets users visualize the effectiveness of their randomization constraints by generating statistical reports on the generated packets. "For anybody who has the TCP/IP protocol, this will generate packets that can be entered into the RTL environment," Khan said. "This is functional coverage, not line coverage. Based on how the RTL interacts with these packets, you can see if any areas are not covered from a functionality standpoint." The packet generator does not require a license, or attendance at one of the company's workshops.
|
Related Semiconductor IP
- Root of Trust (RoT)
- Fixed Point Doppler Channel IP core
- Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)
- Polyphase Video Scaler
- Compact, low-power, 8bit ADC on GF 22nm FDX
Related News
- Free processor firm discloses business plans
- Aldec and SynthWorks deliver Randomization and Functional Coverage Capabilities to VHDL Designers with OS-VVM
- Agnisys Offers Free Register Generator for UVM
- Mirabilis Design is making the standard training class on Model-based System Simulation and Electronic System-Level Design for free
Latest News
- How hardware-assisted verification (HAV) transforms EDA workflows
- BrainChip Provides Low-Power Neuromorphic Processing for Quantum Ventura’s Cyberthreat Intelligence Tool
- Ultra Accelerator Link Consortium (UALink) Welcomes Alibaba, Apple and Synopsys to Board of Directors
- CAST to Enter the Post-Quantum Cryptography Era with New KiviPQC-KEM IP Core
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology