Synopsys unveils synthesis technology to improve FPGA design cycle

Synopsys unveils synthesis technology to improve FPGA design cycle
By Semiconductor Business News
April 19, 2000 (10:43 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000419S0008

MOUNTAIN VIEW, Calif. -- Synopsys Inc. here today released a new technology for FPGA synthesis that it said dramatically reduces the design cycle for multimillion-gate devices.

Block-Level Incremental Synthesis (BLIS), released as part of both FPGA Compiler II and FPGA Express version 3.4, was developed in partnership with Xilinx Inc. BLIS will also be available exclusively to Xilinx customers for nine months in the next version of the Xilinx Foundation Series software release.

"This is a groundbreaking incremental synthesis technology which enables the designer to quickly implement late arriving design changes, without having to re-synthesize the entire design, and potentially save weeks of design re-work," said Jay Michlin, Synopsys' vice president and general manager of the FPGA business unit.

BLIS allows FPGA designers to modify and re-optimize individual blocks in a previously routed design, export these re-optimized blocks as distinct and separate netlists, and execute a guided place-and-route only on the modified sections of the previously routed design. It automatically recalculates timing across the entire design, including taking into account the unmodified portions of the design. Users no longer have to re-synthesize the entire chip, repeat a full place and route, and conduct complex manual re-optimization of the design.

"With the increase in the FPGA densities and intense time-to-market pressure, often design implementation and verification are performed in parallel, resulting in design changes late in the design cycle," said Rich Sevcik, senior vice president of service, IP solutions, and software at San Jose-based Xilinx. "This new methodology enables late-stage design modifications while maintaining the timing for the remaining portion of the design. BLIS is an indispensable capability for designers."

Synopsys is also offering FPGA Compiler II and FPGA Express 3.4 with significantly improved timing accuracy for Altera C orp. APEX 20K devices. "There is a dramatic increase in correlation between the post-synthesis and post-place-and-route timing when using FPGA Compiler IIand FPGA Express version 3.4 to target Altera's APEX 20K devices," said David Greenfield, Altera's director of development tools marketing and product planning, based in San Jose.

Block Level Incremental Synthesis technology is available now directly from Synopsys and will be integrated into the next generation of Xilinx Foundation Series software due this quarter, and starts at $1,995.