Sequence tool performs interconnect-driven timing closure

Sequence tool performs interconnect-driven timing closure
By Michael Santarini, EE Times
September 11, 2000 (11:04 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000911S0017

SAN MATEO, Calif. — Sequence Design Inc. becomes the latest contender in a growing list of companies offering timing-closure tools for system-on-chip designs, with the announcement this week of Copernicus, its interconnect-driven timing optimizer.

While the new tool enters a crowded timing-closure tool market featuring such players as Synopsys Inc., Cadence Design Systems Inc., Magma Design Automation Inc., Monterey Design Systems Inc., and Sapphire Design Automation Inc., the company contends that Copernicus does not directly compete with those companies' offerings because it performs single-pass timing closure after place and route.

Eric Filseth, vice president of product marketing for Sequence (San Jose, Calif.), said that for designs above 0.18 micron, timing problems were largely caused by gate capacitance, which could be handled adequately by the traditional flow of Synopsys' Design Compiler to either Cadence or Avanti Corp. place and route.

But in the sub-0.18-micron age, Filseth said timing problems are caused by capacitance in interconnect as well as in gates, taxing the older ASIC tool flow and driving users to search for timing-closure solutions.

Sequence says Copernicus will fix timing problems in one pass without requiring users to swap out their current tools for new ones.

Alain Labat, president and chief executive officer of Sequence, said Copernicus was built from scratch, and has been in the works at Sequence for over a year and a half.

Filseth said the group at Sequence created a patent-pending post-layout optimization method in Copernicus that achieves timing closure on designs at 0.18 micron and below, at higher clock speeds than achievable using other timing-closure approaches.

Filseth said that most timing solutions that link synthesis closely with placement use a traditional "logic-driven approach" to handle gate and wire capacitance. These approaches create gates, then create gates driving wires using wire-load models and placement-based wire estimates, then perform partial routing; and finally create wires, he said.

"Most timing issues occur because of delays in interconnect, and we don't really know about these delays until final routing is complete," said Filseth. "So what we said was, let's go to an interconnect-driven timing-closure approach."

In the Sequence flow, traditional synthesis-and-place tools create gates and then create wires. Copernicus takes over and creates the gates that are driving the wires.

Users feed .lib, LEF and DEF files as well as constraints in the tool. Copernicus then runs 3-D interconnect modeling, delay calculation, timing analysis, and topology-based optimization. The tool outputs a list of place-and-route directives. The result of the code spit out by this place-and-route run, according to Filseth, will have a 15 to 20 percent better timing for a 0.18-micro n design and a 5 to 15 percent smaller die size.

Gary Smith, chief EDA analyst with Dataquest Inc. (San Jose, Calif.), said Sequence's Copernicus seems to be good technology but has a "limited market window."

"I think the Copernicus technology looks good, at least for the time being," said Smith. "It is cleaning up the timing mess caused by the older Synopsys, Cadence and Avanti flow, but once the new silicon implementation tools really hit the mainstream in a year or so, users probably won't need Copernicus. Right now, however, it looks really good."

Vic Kulkarni, chief operating officer at Sequence, said Copernicus improves the traditional flow and performs timing closure better than any competing tools on the market. "The technology is not going to stand still over the next year," said Kulkarni. "We are going to keep investing in it."

Filseth said the tool makes its largest improvements to the established Synopsys, Cadence and Avanti flows, but said the tool also has been benchmarked by be ta customers with traditional and new flows that incorporated competing timing-closure tools.

Customer benchmark

In all cases, said Filseth, Sequence's tool came out on top. In the customer benchmark, Copernicus showed a 12 percent better timing than competing timing-closure tools run in a Physical Compiler and Silicon Ensemble flow on a 0.25-micron design.

It also showed 28 percent and 14 percent better timing than competing timing-closure tools when used in a traditional Synopsys Design Compiler and Cadence Silicon Ensemble flow on two 0.18-micron designs and 14 percent better timing than competing timing closure tools running in a Design Compiler to Avanti flow on a 0.35-micron design.

"We think this technology represents a fundamental shift in the way people do timing closure," said Filseth.

Copernicus running on Unix is priced at $187,500 for a one-year license.