Prosilog and OCP-IP announce a family of OCP compliant AMBA and corconnect bridges
Cergy, France, and Portland, ORE. – August 18, 2003 –
Prosilog SA, the leading provider of innovative solutions for SoC design and verification, and Open Core Protocol International Partnership (OCP-IP) announce the availability of a family of OCP compliant bridges for the AMBA and CoreConnect protocols. The bridges support integration and analysis of heterogeneous systems with multiple processors and buses. As a result, for a given OCP compliant IP, Prosilog delivers a configurable adapter, to bridge between the IP and any AMBA or CoreConnect bus.
As an active member of the System Level Design Working Group in OCP-IP, Prosilog works with other members such as Nokia, Sonics, Synopsys and Texas Instruments to address problems relating to design, verification and testing which are common to IP core reuse in "plug and play" system-on-chip (SoC) products and make “bus-independent IP” a reality.
“Prosilog’s adapters are part of a robust infrastructure surrounding OCP, ensuring a complete socket standard that everyone can use, no matter what their on-chip architecture is, or whose processor cores they're using,” said Ian Mackintosh, president, OCP-IP. “We are extremely proud of the work done by Prosilog as part of OCP-IP’s System Level Design Working Group.”
This set of bridges from Prosilog is included into the Magillem environment (platform generation and IP integration tool) as well as into Prosilog’s IP portfolio.
About OCP-IP
The OCP International Partnership Association, Inc. (OCP-IP) was announced in December 2001 to promote and support the open core protocol (OCP) as the complete socket standard that ensures rapid creation and integration of interoperable virtual components. OCP-IP's Governing Steering
Committee participants are: Nokia [NYSE: NOK,], Texas Instruments [NYSE: TXN], ST Microelectronics [NYSE: STM], United Microelectronics Corporation [NYSE: UMC], Sonics, and other industry leading companies. OCP-IP is a non-profit corporation delivering the first fully supported, openly licensed core-centric protocol that comprehensively fulfills system-level integration requirements. The OCP facilitates IP core reusability and reduces design time and risk, along with manufacturing costs for SoC designs. For additional background and membership information, visit www.OCPIP.org.
###
Magillem and Nepsys are registered trademarks of Prosilog SA. All other trademarks are the property of their respective holders.
Related Semiconductor IP
- Flash Memory LDPC Decoder IP Core
- SLM Signal Integrity Monitor
- All Digital Fractional-N RF Frequency Synthesizer PLL in GlobalFoundries 22FDX
- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
- TSMC CLN5FF GUCIe LP Die-to-Die PHY
Related News
- Prosilog announces the integration of Yogitech's OCP eVC in Magillem
- Prosilog SA Wins OCP-IP's Outstanding Contributor of the Year Award for 2004
- Denali and OCP-IP Announce the availability of OCP Compliant Databahn Memory Controller Cores
- YogiTech and OCP-IP: new features added to OCP 2.0 eVC
Latest News
- Rapidus Achieves Significant Milestone at its State-of-the-Art Foundry with Prototyping of Leading-Edge 2nm GAA Transistors
- SEMIFIVE Files for Pre-IPO Review on KRX
- Innosilicon Scales LPDDR5X/5/4X/4 and DDR5/4 Combo IPs to 28nm and 22nm, Cementing Its Position as the ‘One Stop’ for Memory Interface Solutions
- Synopsys Completes Acquisition of Ansys
- Zephyr 4.0 Now Available for SCR RISC-V IP