Phison Deploys Cadence Cerebrus AI-Driven Chip Optimization to Accelerate Product Development
January 23, 2024 -- Phison Electronics Corporation is a market leader in NAND Flash controllers and applications, including USB, SD, eMMC, PATA, SATA, PCIe, and UFS. The company has shipped over 600 million controllers worldwide yearly, topping over US 2.2 billion dollars in sales revenue. Recently, Phison successfully deployed the Cadence Cerebrus Intelligent Chip Explorer and the complete Cadence RTL-to-GDS digital full flow to optimize their next-generation 12nm NAND controller ICs. The generative AI technology-based Cadence Cerebrus enabled Phison to automatically reduce the power by 35% and area by 3% in a multi-million cell flash controller block.
To accelerate product development, Phison used Cadence Cerebrus with a specific focus on power and area. Cadence Cerebrus and the broader digital full flow—including Cadence’s Genus Synthesis Solution, Innovus Implementation System, and Tempus Timing Solution—provide optimal power, performance, and area (PPA) and faster turnaround time, enabling system-on-chip (SoC) design excellence.
“Chip area and power consumption are critical differentiators for our NAND controller ICs,” said Vincent Cheng, VP of engineering, Phison. “By adopting the Cadence Cerebrus generative AI technology, we can now rapidly optimize die area and power, enabling Phison to deliver more competitive products to our customers.”
Dr. Venkat Thanvantri, corporate vice president of AI R&D at Cadence said, “Cadence Cerebrus automatically reduced power by 35% on Phison’s designs in just one week, which clearly demonstrates how generative AI can improve results and productivity.”
The Phison design team successfully achieved their PPA goals significantly quicker than traditional manual design optimization using Cadence Cerebrus Intelligent Chip Explorer. The generative AI capability of Cadence Cerebrus helped Phison to achieve the desired results automatically in just one week. In addition to power and area optimizations, Cadence Cerebrus simultaneously reduced the turnaround time and helped Phison deliver higher-quality products much faster.
Related Semiconductor IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- ASIL B Compliant MIPI CSI-2 CSE2 Security Module
- SHA-256 Secure Hash Algorithm IP Core
- EdDSA Curve25519 signature generation engine
Related News
- Imagination Optimizes PPA and Speeds the Delivery of Low-Power GPUs Using AI-Driven Cadence Cerebrus in the OnCloud Platform
- Transforming Chip Design with Agentic AI: Introducing Cadence Cerebrus AI Studio
- Cadence Revolutionizes System Design with Optimality Explorer for AI-Driven Optimization of Electronic Systems
- Cadence Collaborates with Arm to Accelerate Neoverse V2 Data Center Design Success with Cadence AI-driven Flows
Latest News
- Analog Bits Demonstrates Real-Time On-Chip Power Sensing and Delivery on TSMC N2P Process at TSMC 2026 Technology Symposiums
- TES offers a High-Frequency Synthesizer and Clock Generator IP for X-FAB XT018 - 0.18µm BCD-on-SOI technology
- Faraday Delivers IP Solutions to Enable Endpoint AI Based on UMC’s 28nm SST eFlash
- AiM Future Partners with Metsakuur Company to Commercialize NPU-Integrated Hardware
- ESD Alliance Reports Electronic System Design Industry Posts $5.5 Billion in Revenue in Q4 2025