Morpho Technologies demonstrates 3G software defined radiorunning in silicon
Irvine, CA., March 31, 2003 - Morpho Technologies successfully demonstrates a complete software 3G baseband processor running on the MS1-64 reconfigurable Digital Signal Processor (rDSP) at the GSPx & International Signal Processing Conference, March 31 through April 3rd. Morpho Technologies’ MS1 rDSP implements the baseband functions of a WCDMA Transceiver for handsets and infrastructure equipment while simultaneously running applications such as MPEG4, GPS, 802.11, as well as others. The MS1 rDSP executes these applications by running programs residing in flash memory outside the chip.
The MS1 core meets the needs of both current and emerging wireless demands for both handsets and base stations allowing customers to rapidly develop and launch new products featuring the latest algorithms supporting a wide array of standards and remotely deploy upgrades as standards evolve and new software technologies become available.
Two versions of the MS1 architecture, the MS1-64 and MS1-16, running in hardware development systems are currently available from Morpho Technologies. These devices represent the most advanced Software Defined Radio (SDR) and multimedia solutions available to the communications community.
The MS1-16 and MS1-64 DSPs are multiple element processing arrays designed to provide processing capacity required by multimode wireless terminal designs that implement multiple wireless standards together with multiple data processing applications. Examples include WCDMA/CDMA, GSM/GPRS/EDGE, 802.11, GPS, image processing for both still and motion pictures including MPEG and JPEG, voice processors, and audio processing including MP3.
The programmability of the MS1 architecture supports the rapid implementation of wireless standards including 3GPP and 3GPP2 releases. As these standards evolve, off-chip software modifications eliminate the need for new ASIC devices, resulting in a significant reduction in design time as well as a risk reduction in making baseband processor chips. With the new technologies from Morpho Technologies, portable device and infrastructure manufacturers can build products and know they can easily be upgraded and modified, even if they have to sit in inventory for a while.
"The MS1-16 and MS1-64 reconfigurable DSP cores enable our customers to develop products with less cost and less risk compared to traditional ASIC development techniques,” comments Todd Nash, Vice President, Business Development, Morpho Technologies. "The processing capacity, power efficiency, and flexibility of the MS1 architecture enable manufacturers to rapidly move from prototype to product introduction."
Related Semiconductor IP
- 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
- 1.8V/3.3V I/O Library with ODIO and 5V HPD in TSMC 12nm
- 1.8V to 5V GPIO, 1.8V to 5V Analog in TSMC 180nm BCD
- 1.8V/3.3V GPIO Library with HDMI, Aanlog & LVDS Cells in TSMC 22nm
- Specialed 20V Analog I/O in TSMC 55nm
Related News
- Morpho Technologies demonstrates MPEG-4 video for 2.5G and 3G wireless applications
- Omni Design Technologies Offers Swift™ Data Converters for Advanced Software Defined Radio (SDR) Solutions
- Siemens to demonstrate first pre-silicon simulation environment for Arm Cortex-A720AE for Software Defined Vehicles
- Siemens delivers end-to-end silicon quality assurance for next-generation IC designs with new Solido IP Validation Suite
Latest News
- Will RISC-V reduce auto MCU’s future risk?
- Frontgrade Gaisler Launches New GRAIN Line and Wins SNSA Contract to Commercialize First Energy-Efficient Neuromorphic AI for Space Applications
- Continuous-Variable Quantum Key Distribution (CV-QKD) system demonstration
- Latest intoPIX JPEG XS Codec Powers FOR-A’s FA-1616 for Efficient IP Production at NAB 2025
- VeriSilicon Launches ISP9000: The Next-Generation AI-Embedded ISP for Intelligent Vision Applications