Micron Tells Story of Building DRAM Cube
Rick Merritt, EETimes
8/13/2013 08:03 PM EDT
SAN JOSE, Calif. — Micron's Hybrid Memory Cube -- a 4 GByte stack of DRAM die on a 160 GByte/second interface now sampling to a few close partners -- almost didn't happen. The first prototype failed to make connections between the DRAM stack and a controller inside the package, forcing an all-hands-on-deck effort to save the project.
Two top engineering managers leading the program told some of the story behind the Cube in an interview with EE Times. They also shared a few of their goals for the next-generation chip now in the works -- an 8 GByte stack transferring data at up to 320 GBytes/second with even greater power efficiency that the current samples.
The Cube got its start in early 2006 when the industry was buzzing with talk both about multicore processors and 3D chip stacks using through silicon vias (TSVs).
To read the full article, click here
Related Semiconductor IP
- Low Latency DRAM Synthesizable Transactor
- Low Latency DRAM Memory Model
- DDRx & LPDDRx DRAM Memory Controller - TSMC 12nm 12FFC,FFC+
- DDRx & LPDDRx DRAM Memory Controller - TSMC 16nm 16FFC,FF
- DDRx & LPDDRx DRAM Combo Memory Controller
Related News
- Micron Announces Its First Fully Functional DDR4 DRAM Module
- Altera and Micron Lead Industry with FPGA and Hybrid Memory Cube Interoperability
- Micron Technology Ships First Samples of Hybrid Memory Cube
- eASIC Completes Tapeout of 0.13 micron Configurable Platform
Latest News
- Jim Keller: ‘Whatever Nvidia Does, We’ll Do The Opposite’
- FlexGen Streamlines NoC Design as AI Demands Grow
- IntoPIX Presents Its New Titanium Software Suite: Empowering AV-Over-IP Workflows With Speed, Quality & Interoperability
- Global Semiconductor Sales Increase 2.5% Month-to-Month in April
- Speedata Raises $44M to Launch First-Ever Chip Designed Specifically for Accelerating Big Data Analytics - Compute's Second Largest Workload