Microchip develops new flash technology to cut cost of re-programmable MCUs
![]() |
Microchip develops new flash technology to cut cost of re-programmable MCUs
By Semiconductor Business News
September 4, 2001 (2:09 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010904S0060
CHANDLER, Ariz.--Microchip Technology Inc. today disclosed a new flash memory technology, which promises to drive down the cost of flash-based microcontrollers to the range of one-time programmable (OTP) MCUs. The technology also will increase the endurance of the nonvolatile, re-programmable flash in 8-bit microcontrollers, according to the company. Also today, Microchip launched 14 new flash-based microcontrollers, based on the patented technology. The company said it plans to introduce another 16 devices based on the process technology during the next six months as it expands its offering in embedded markets. The Chandler-based company disclosed the new flash technology and microcontrollers during the opening of the Embedded Systems Conference in Boston today. Microchip president and CEO Steve Sanghi compared the new technology and rollout of MCUs to his company's efforts to drive down the cost of OTP-based MCUs. "We're taking that same philosophy and technical expertise to make flash microcontrollers cost effective for mainstream embedded applications," he said. The company's new flash process technology features a patented PMOS electrically erasable Cell, called PEEC. The cell is the result of three years of development, and it's three times smaller than previous-generation EEPROMs, according to Microchip. Microchip said the PEEC cell utilizes a size-reduced merged cell with a Fowler Nordheim tunneling region instead of a defined tunnel dielectric window. This approach improves manufacturability, repeatability and reliability across a temperature range of -40 degrees C to +125 degrees C. It also supports 2.0 to 5.5 volt Vdd operations, the company said. Tests have shown devices capable of more than 5 million erase/write cycles and greater than 40 years of data retention, Microchip said. According to the company, this high level of reliability characterization and manufacturability will enable microcontroller system designers t o achieve more than 1 million data memory erase/write cycles and more than 100,000 program memory cycles. The on-chip erase/write charge pump allows for full erase/write/read operations at only 2.0 volts without an external Vpp voltage, Microchip said. I/O voltages used in this technology are true 5.5V capable, said the MCU supplier. Microchip is aiming the technology at an 8-bit flash-based microcontroller market that's expected to grow from $600 million in 2000 to $1.5 billion in 2003. The embedded applications cover the gamut--everything from automotive subsystems to networked home appliances to medical systems, parking meters, and vending machines.
Related Semiconductor IP
- SLVS Transceiver in TSMC 28nm
- 0.9V/2.5V I/O Library in TSMC 55nm
- 1.8V/3.3V Multi-Voltage GPIO in TSMC 28nm
- 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
- ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
Related News
- Cut Down Silicon Cost with SWORD - the Single Wire Debugging Solution from Evatronix
- Lattice Programmable Power Manager Device Reduces Cost of Power Failure Protection for Solid State Drives
- TOSHIBA Develops High Speed NANO FLASH-100 Flash Memory for ARM Core Based Microcontrollers
- Lattice Announces MachXO3 FPGA Family; Most Advanced, Lowest Cost per I/O Programmable Bridging and I/O Expansion Solution
Latest News
- Latest intoPIX JPEG XS Codec Powers FOR-A’s FA-1616 for Efficient IP Production at NAB 2025
- VeriSilicon Launches ISP9000: The Next-Generation AI-Embedded ISP for Intelligent Vision Applications
- GUC Announces Tape-Out of the World's First HBM4 IP on TSMC N3P
- lowRISC and SCI Semiconductor Release Sunburst Chip Repository for Secure Microcontroller Development
- BrainChip Partners with RTX’s Raytheon for AFRL Radar Contract