Mentor ports design-for-test tools to 64 bits

Mentor ports design-for-test tools to 64 bits
By Stan Runyon, EE Times
March 28, 2000 (10:02 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000328S0006

PARIS — Mentor Graphics Corp. rolled out the first 64-bit automatic test pattern generator (ATPG) tool suite today at the Design Automation and Test Europe (Date) 2000 Conference.

An enhanced version of the company's FastScan tool, it runs on Sun Microsystems' 64-bit Solaris and Hewlett-Packard's 64-bit platform.

Mentor also said it is porting other design-for-test tools to 64 bits, including FlexTest, DFTAdvisor and DFTInsight. Several of the company's front-end system-on-chip design suites already are available on 64-bit architectures.

David Stannard, Mentor's ATPG product manager, said these 64-bit tools target not speed but capacity. "We've reached the point at which designs are too large to fit into the 32-bit addressing space," he said.

Gary Smith, an analyst with Dataquest Inc., concurred. "You cannot design a 5-million-gate ASIC on a 32-bit operating system," he said. "Memory requirements alone are a deciding factor."

B ut there should be some productivity gains to the designer, who now may avoid some partitioning, multiple runs or model changes forced by lack of capacity. Also, there is the increasing probability that long scan chains or clock domains — a trend — can be stitched together in a single pass. "We recently saw a design that had 100,000 scan elements," Stannard said.

The inflection point for going to 64 bits, he said, kicks in at 3 million or 4 million gates.

"We've seen that in other products porting to 64 bits," said Fred James, the EDA segment manager at Sun Microsystems. "That is, users are not required to partition the larger designs."