Lexra fires 32-bit volley in CPU core war

Lexra fires 32-bit volley in CPU core war
By Anthony Cataldo, EE Times
April 23, 2001 (10:30 a.m. EST)
URL: http://www.eetimes.com/story/OEG20010423S0047

SAN MATEO, Calif. — As it prepares to ward off a legal attack from rival MIPS Technologies Inc., scrappy processor-core vendor Lexra Inc. is mounting its own offensive in the 32-bit processor arena.

Lexra is so confident of its forthcoming third-generation 32-bit processor that it is planning to charge a premium over comparable 32-bit cores from MIPS, an unusual tactic for a company that still considers itself an underdog.

"We've won some business against MIPS' 4k core and we've won business from MIPS' existing licensees," said Charlie Cheng, president and chief executive officer of Lexra (San Jose, Calif.). "That has given us some confidence. We understand their road map and we know there's a gap there we want to capitalize on."

That gap, Cheng believes, lies somewhere between 32- and 64-bit processing. While MIPS' top-shelf processors are in the 64-bit realm, Lexra is betting that it can compete by fielding a performance-enhanced 32-bit processor that's compatible with the MIPS16 instruction-set architecture.

Though Cheng is the first to admit his company hasn't the resources to match MIPS, he said Lexra, which has 30 licensees, will act like its equal at the negotiating table. The nonrecurring engineering costs for the LX4380, which will be available in the third quarter, are $568,000. "My guess is we're $100,000 more expensive [than MIPS] on a per-project basis," Cheng said.

As for royalties, Lexra aims to charge 85 cents per chip based on quantities of 100,000 units.

Cheng also claimed that the LX4380 will be shielded from legal attacks by MIPS Technologies because Lexra has removed the capability to do software emulation of unaligned loads and stores. Rather, Lexra said it will use the open-source Linux operating system, which Cheng said can be recompiled without these instructions.

Legal hearing

MIPS Technologies claims that Lex ra, which has not taken a MIPS instruction-set license, has infringed patents covering unaligned load/stores and extended-precision arithmetic. A judge is expected to hear the case on Wednesday (April 25) in a preliminary hearing at the U.S. District Court for the Northern District of California, in Oakland.

With the LX4380, which is specified for 0.13-micron design rules, Lexra has extended its processor pipeline to seven stages, two more than its existing RISC cores. That has allowed the company to push frequency to 300 MHz, vs. 166 MHz for its current devices.

Lengthening the pipelining also gave the instruction and data memory more cycles to work with, allowing customers to use off-the-shelf 32-kbyte instruction and data caches rather than handcrafted RAM. Lexra also replaced its write-through cache with a write-back cache. That's more efficient, Cheng said, because data is held close to the CPU longer and doesn't have to write back to main memory as frequently.

As part of the redesign, the company repartitioned the processor modules to simplify the control and data paths. It also got rid of the monolithic CPU and system clock, which Cheng called a "four-year-old mistake," and added a mechanism to divide the clock internally. Under this scheme, the system bus now runs at half the speed of the CPU and can handle slower custom logic.

Because many of the embedded applications Lexra is targeting are data intensive, the CPU spends as much as 10 percent of its cycles sitting idle while it waits for data transfers, Cheng said.

To mitigate this problem, Lexra added twin-registers that enabled the CPU to load pairs of registers in a single-cycle operation "so that it looks like 64-bit," Cheng said.

Finally, to reduce bus latencies, the company added what it calls a "block move controller" that manages traffic among the peripherals, instruction and data memory, and the CPU core.