Leopard Logic Unveils RapidIO Implementation Platform Based on its HyperBlox Embedded Cores

Cupertino, CA – July 15, 2002 – Leopard Logic, Inc. today announced the availability of a RapidIO™ platform based on its HyperBlox™ embedded FPGA cores. The platform supports the RapidIO 1x/4x LP-Serial interface (Rev. 1.1), enabling data rates of up to 20 Gbps. Customers using Leopard Logic’s cores can start with the implementation of designs targeting RapidIO immediately, while the specification is still awaiting final ratification and changes are still possible.

The platform is built around an embedded FPGA core that is used to implement the control and protocol logic which are still likely to change as the standard matures, while timing critical blocks such as 8B/10B SERDES, PLLs and well defined functions like CRC checks, memories and register files are implemented in standard cells. Using Leopard Logic’s high performance HyperBlox cores allows designers to fully support the RapidIO interface standard from single lane 800Mbps interfaces up to a 4 lane 10Gpbs solution. "The use of an FPGA-based implementation for evolving standards enables our customers to get a head start and design chips well before the final ratification of the technical specifications. The flexibility of our solution even allows for late changes in case interoperability problems arise between implementations from different manufacturers,” said Stefan Tamme, Leopard Logic’s vice president of sales and marketing.

Embedded FPGA cores for emerging or evolving standards offer a number of benefits compared to a hardwired implementation:

1. Early Implementation Start

Standards are often driven by a number of technical and commercial factors. Sometimes, strong industry players may influence specifications late in the process. With a traditional hardwired implementation in standard cells, such late specification changes can cost months of design time or worse - may render a complete design useless if already in production. The most likely changes are usually in the protocol and control logic of a design. By implementing the critical state machines in the FPGA core, such risks can be eliminated because only the architecture and partitioning of the design needs to be fixed, while the actual implementation remains flexible, even after production.

2. Interoperability Insurance 

The use of programmable logic for critical portions of a design helps mitigate interoperability risks. With the increasing complexity of interface standards, the risk of interoperability problems increases dramatically. By keeping portions of the design flexible, chips can be easily adopted to work with devices from different vendors by just downloading different configuration bitstreams. The use of an embedded FPGA core removes the need to go off chip to an external FPGA, allowing users to meet the performance specifications of high-speed serial IO standards such as RapidIO.

3. Multi-Standard Silicon Platforms

Leopard Logic is committed to providing advanced platforms to its licensees. Other emerging standards such as PCI Express (formerly 3GIO) or HyperTransport are currently under investigation. They could be implemented using the same platform architecture, and may be supported at a later time based on market requirements. By using flexible partitioning, the HyperBlox based platform facilitates multi-standard implementations in the same silicon.

Embedded FPGA cores enable the amortization of rapidly increasing design and mask costs over larger product volume, while completely eliminating the costs for derivative products that can be generated by configuring the same device with different bitstreams.

For semiconductor companies, embedded FPGAs provide an effective means to capture more of the silicon content of the final product by eliminating the need for standalone FPGA devices in many cases. System c ompanies can get the same functionality at an order of magnitude lower price point, significantly reducing the BOM (bill of materials) for a given product.

At the same time, the use of a single-chip implementation provides a smaller footprint and reduces power, while increasing the speed compared to standard FPGAs. At the 90nm process node, the use of pre-verified configurable blocks will help to dramatically shorten the lengthy and painful timing closure process and to minimize the impact of other deep sub-micron effects such as cross-talk and electro migration.

About Leopard Logic, Inc.

Leopard Logic provides embedded FPGA solutions that increase performance and flexibility while reducing risk and system costs for System-on-Chip devices. Used to create next generation programmable device platforms, Leopard Logic's cores are ideally suited for DSP or packet processing intensive applications targeting markets like communication infrastructure and network access. The cores are silicon proven in leading manufacturing processes from TSMC and are delivered with a comprehensive integration package, including a suite of optimized software tools, enabling rapid integration with industry standard design flows and third party EDA tools. For more information visit www.leopardlogic.com .