Japan solidifies structure of SoC research group Mirai

Japan solidifies structure of SoC research group Mirai
By Paul Kallender, EE Times
July 27, 2001 (12:07 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010724S0076

TOKYO — Mirai, Japan's research juggernaut aimed at developing system-on-chip (SoC) process technologies for the 70-nm and 50-nm nodes, must deliver results that will help Japan take a 25 percent market share of the world semiconductor market in the second half of this decade, the project's director said Tuesday (July 24).

Speaking at a press conference outlining the project's structure ahead of its research launch this August, director Masataka Hirose said Mirai will concentrate on five research areas commanded by project leaders who should cast away old practices, encourage risk-taking and, above all, deliver results.

"In the context of the worldwide race for new semiconductor technology development, we are determined to make clear achievements that meet the needs of industry, especially during the first three-year phase," Hirose said.

Those five projects, Hirose said, will focus on gate technology for high-K materials, wiring module technology with low-K, new transistor structures and measurement analysis technologies, lithography and circuit system technology.

The targets, to develop 70-nm-process technology ready for SoC products development in 2004 and 50-nm-process technology for SoC products in 2008, were tight but achievable, he said, because of new efficiencies built into Mirai's research structure.

Hirose said the need to meet these targets is critical to the future of Japan's semiconductor industry, which needs to aim at capturing a quarter of the world's market for SoC on or after 2005. Hirose estimated the world market for SoCs would pass the $200 billion mark in 2005 and $400 billion in 2008. But, just as important, that market would more than double again to pass $900 billion in 2011.

"We have to have a 'let's do it all' approach. In 10 years the market for SoC devices will more than quadruple. We should aim at taking a quarter of this, but whether we can do it or not depends on our technology, our products and our vision," he said.

Mirai is Japan's answer to IMEC, International Sematech and the EUV LLC consortium all rolled into one. Industry, academia and bureaucracy are participating in the project to ensure that Japan keeps up with its International Technology Roadmap for Semiconductors.

Mirai will kick off this August with $30.6 million in funding provided by the Ministry of Economy, International Trade and Industry's New Energy and Industrial Technology Organization (Nedo). The Millennium Research for Advanced Information Technology, as Mirai is formally known, also builds on the work of several other industry-academic-governmental research consortiums. These include the Semiconductor Leading Edge Technologies Inc. (Selete) project to develop system-on-chip technologies and Asuka, Mirai's ongoing predecessor project, which is developing process technologies beyond the 100-nm node.

While those two projects will feed into Mirai, the project will be controlled by other bodies: the Advanced Semico nductor Research Center(ASRC), of which Hirose is director, and the National Institute of Advanced Industrial Science and Technology. With a staff of 3,200, ASRC is a subdivision of a new research body, the Institute of Advanced Industrial Science and Technology (AIST), which, in turn, is itself an integration of 15 research institutes.

But the result of all this reformulation will not be turf wars and paper shuffling, Hirose said. Despite the ever more complex soup of organizations swirling around the project's core, Hirose was adamant that, in particular, Mirai's results-based research management structure would differentiate it from standard government-backed research initiatives. Such research initiatives have often been criticized here because they are seen to be weighed down by bureaucracy and produce meritorious but dead-end technologies compared with Japan's product-oriented industry labs.

Promoting something that is still rare in Japan, each of the five project's leaders will be given dire ct responsibility and executive decision-making powers to pursue or to scrap ideas for the projects, said Hirose. The project will shelve Japan's notoriously hierarchical, even tribal, research culture and replace it with a flat structure that will give off-the-wall ideas a chance. Each project will also have to regularly present its progress to outside monitoring committees.

"We want Mirai to become one of the top three [semiconductor research consortiums] in the world," Hirose said, specifically noting that while the Mirai project was starting later than other international consortiums, it could catch up.

"We'll do our best, we'll put all our energy together to hit the targets," promised Toshiaki Masuhara, executive director of the National Institute of Advanced Industrial Science and Technology, who, like Koichi Nagasawa, president of Mitsubishi Electric Corp.'s Semiconductor Group, chimed in with support for the project. Nagasawa told EE Times that the crucial nature of the project requi red Japan's semiconductor giants to combine their intellectual property on their proprietary processes to come up with a common platform technology from which everyone could benefit.

Hard data and concrete results can't come until Mirai gets access to Japan's seven-story, $200 million super clean room, said Seichi Kawamura, who is vice director at ASRC. Mirai will be sharing the 3,000 square meters of Clean Level 1 research space with the Asuka project when the facility, which is based in Tsukuba Science City north of Tokyo, opens next March.

Before that, the five research teams will spend the summer in intensive consultations deciding how they are going to utilize the space, said Kawamura, who is responsible for coordinating the five projects under Hirose for Mirai.

"We'll be ready to discuss more specifics in an October-November time frame," said Kawamura.