IP Cores, Inc. Announces New Multi-Gigabit IP Combo AES/XEX and AES/GCM Core Supporting New IEEE P1619 Draft Standard
IP Cores, Inc. announces silicon IP core supporting new industry standards. Starting at 60K ASIC gates and delivering up to 10 Gbps throughput, GXM3 cores provides a compact and efficient solution for an SoC designer working on a secure IEEE P1619 storage or IEEE 802.1AE networking solution.
Palo Alto, California, November 23, 2006 -- IP Cores, Inc., setting the benchmark for security IP cores, today announced new silicon IP core supporting new draft of the P1619.1 disk drive encryption standard and shipped it to customer. The new GXM3 core enables System on Chip (SoC) vendors to build compact cryptographic processors that support the AES/XEX and AES/GCM cryptographic algorithms.
"The IEEE P1619 standardization group has recently decided to drop the LRW mode of the AES cipher and adopt the new XEX mode in its new draft. With the shipment of the GXM3 combo core we became the first IP vendor to announce shipment of a combined GCM/XEX core," said Dmitri Varsanofiev, CTO of IP Cores. "Our IP customers will convert the early access to GXM3 into a competitive advantage for their networked storage solutions. "
High-speed Encryption Protects Data in Storage and inside the Network
Advanced Encryption Standard (AES) is recently used to provide data security in storage, both on a hard drive or tape and on the network. Addressing the market demand for integrated high-speed AES crypto solutions for these two markets, IP Cores’ GXM3 supports the AES/XEX and AES/GCM modes in a single core. GXM3 supports 128-bit and 256-bit keys for design flexibility. GXM3 is designed for throughput of 25.6 Mbits per MHz.
AES in XEX encryption mode is highly parallelizable used in the IEEE standard P1619 for narrow-block hard disk encryption. GXM3 also includes the AES/GCM cipher designed to provide data security and authentication. AES in GCM mode allows parallel authentication implementations and therefore can be used for communication channels that require very high-speed authenticated encryption, such as supporting IEEE 802.1AE security for Ethernet networks, or IPsec RFC 4106. GXM3 configurations support AES/GCM and AES/LRW authenticated encryption throughput up to 10 Gbps in a single core using 130 and 90 nm processes, with easy parallelization. Gate count for a fully self-contained GXM3 starts at 60K gates.
GXM3 contributes to the IP Cores’ efficient portfolio of AES-based security IP cores. Cores are available in multiple configurations to meet specific SoC throughput, power, and gate count goals. For more information about IP Cores’ product line, please visit www.ipcores.com.
About IP Cores, Inc.
IP Cores is a fast-moving company in the field of security IP cores. Founded 2 years ago, the company provides IP cores to protect communications and intellectual property.
Related Semiconductor IP
- Multi-channel, multi-rate Ethernet aggregator - 10G to 400G AX (e.g., AI)
- Multi-channel, multi-rate Ethernet aggregator - 10G to 800G DX
- 200G/400G/800G Ethernet PCS/FEC
- 50G/100G MAC/PCS/FEC
- 25G/10G/SGMII/ 1000BASE-X PCS and MAC
Related News
- IP Cores, Inc. Announces New High-Speed IP Combo XEX-AES Family of Cores Supporting New IEEE P1619 Draft Standard
- IP Cores, Inc. Shipped Ultracompact AES and AES/GCM IP Cores for Actel FPGA Supporting FIPS-197, IEEE 802.1AE MACsec and P1619.1 Standards
- Ceva Unveils Ceva-Waves Links200 - A Breakthrough Multi-Protocol Wireless Connectivity Platform IP Featuring Next generation Bluetooth High Data Throughput (HDT) and IEEE 802.15.4
- IP Cores, Inc. Announces a Family of Low-Latency AES/GCM IP Cores Supporting IEEE 802.11ad and WiGig Standards
Latest News
- How CXL 3.1 and PCIe 6.2 are Redefining Compute Efficiency
- Secure-IC at Computex 2025: Enabling Trust in AI, Chiplets, and Quantum-Ready Systems
- Automotive Industry Charts New Course with RISC-V
- Xiphera Partners with Siemens Cre8Ventures to Strengthen Automotive Security and Support EU Chips Act Sovereignty Goals
- NY CREATES and Fraunhofer Institute Announce Joint Development Agreement to Advance Memory Devices at the 300mm Wafer Scale