IP And FinFETs At Advanced Nodes - Part 2
Ed Sperling, Semiconductor Engineering
July 21, 2014
Experts at the table, part 2: FinFETs become more complex at each new node; stacked die IP challenges; including the package in the simulation; local versus global design concerns.
Semiconductor Engineering sat down to discuss IP and finFETs at advanced nodes with Warren Savage, president and CEO of IPextreme; Aveek Sarkar, vice president of engineering and product support at Ansys-Apache; Randy Smith, vice president of marketing at Sonics, and Bernard Murphy, CTO of Atrenta;. What follows are excerpts of that conversation.
Related Semiconductor IP
- 6-bit, 12 GSPS Flash ADC - GlobalFoundries 22nm
- LunaNet AFS LDPC Encoder and Decoder IP Core
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
- PDM Receiver/PDM-to-PCM Converter
Related News
- Cadence Partners with TSMC to Power Next-Generation Innovations Using AI Flows and IP for TSMC Advanced Nodes and 3DFabric
- Innosilicon to Showcase High-Speed Interface IP and Advanced SoC Solutions at the 2025 TSMC OIP Ecosystem Forum
- PGC Strengthens Cloud and AI ASIC Acceleration with Synopsys’ Next-Generation Interface and Memory IP on Advanced Nodes
- LTSCT and Andes Technology Sign Strategic IP Licensing Master Agreement to accelerate RISC-V Based Advanced Semiconductor Solutions
Latest News
- Rambus Unveils HBM4E Controller: 16 GT/s, 2,048-Bit Interface, Enabling C-HBM4E
- AimFuture, a Leader in Home Appliance NPUs, to Integrate Mesacure Company’s AI Algorithms
- Security in the Quantum Era: From Cryptography to Trust — ICTK Introduces a Hardware Trust Foundation for the Quantum Era
- TES unveils a next-generation Elliptic Curve Digital Signature Algorithm (ECDSA) IP Core for Secure IoT, Blockchain, and Industrial Systems
- Seligman Ventures Leads Cognichip’s $60M Series A to Back Physics-Informed AI for Chip Design, Intel CEO Lip-Bu Tan and Seligman Ventures’ Umesh Padval Join the Board