IP And FinFETs At Advanced Nodes - Part 2
Ed Sperling, Semiconductor Engineering
July 21, 2014
Experts at the table, part 2: FinFETs become more complex at each new node; stacked die IP challenges; including the package in the simulation; local versus global design concerns.
Semiconductor Engineering sat down to discuss IP and finFETs at advanced nodes with Warren Savage, president and CEO of IPextreme; Aveek Sarkar, vice president of engineering and product support at Ansys-Apache; Randy Smith, vice president of marketing at Sonics, and Bernard Murphy, CTO of Atrenta;. What follows are excerpts of that conversation.
Related Semiconductor IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- 1G BASE-T Ethernet Verification IP
- Network-on-Chip (NoC)
- Microsecond Channel (MSC/MSC-Plus) Controller
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
Related News
- PGC Strengthens Cloud and AI ASIC Acceleration with Synopsys’ Next-Generation Interface and Memory IP on Advanced Nodes
- Innosilicon to Showcase High-Speed Interface IP and Advanced SoC Solutions at the 2025 TSMC OIP Ecosystem Forum
- Cadence Partners with TSMC to Power Next-Generation Innovations Using AI Flows and IP for TSMC Advanced Nodes and 3DFabric
- Kerala Positions Design and IP at Core of Chip Strategy
Latest News
- Virtusa Acquires Bengaluru based SmartSoC Solutions, Establishing Full-Stack Service Offering from Chip to Cloud and Driving Expansion into the Semiconductor Industry
- Consumer Electronics and AI Product Launches Lift 3Q25 Top-10 Foundry Revenue by 8.1%, Says TrendForce
- Joachim Kunkel Joins Quadric Board of Directors
- RaiderChip NPU leads edge LLM benchmarks against GPUs and CPUs in academic research paper
- SEMIFIVE Secures AI Semiconductor Design Projects in Japan, Accelerating Global Expansion with New Local Subsidiary