IP And FinFETs At Advanced Nodes - Part 2
Ed Sperling, Semiconductor Engineering
July 21, 2014
Experts at the table, part 2: FinFETs become more complex at each new node; stacked die IP challenges; including the package in the simulation; local versus global design concerns.
Semiconductor Engineering sat down to discuss IP and finFETs at advanced nodes with Warren Savage, president and CEO of IPextreme; Aveek Sarkar, vice president of engineering and product support at Ansys-Apache; Randy Smith, vice president of marketing at Sonics, and Bernard Murphy, CTO of Atrenta;. What follows are excerpts of that conversation.
Related Semiconductor IP
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- MIPI CSI-2 CSE2 Security Module
- ASIL B Compliant MIPI CSI-2 CSE2 Security Module
Related News
- Cadence Partners with TSMC to Power Next-Generation Innovations Using AI Flows and IP for TSMC Advanced Nodes and 3DFabric
- Innosilicon to Showcase High-Speed Interface IP and Advanced SoC Solutions at the 2025 TSMC OIP Ecosystem Forum
- PGC Strengthens Cloud and AI ASIC Acceleration with Synopsys’ Next-Generation Interface and Memory IP on Advanced Nodes
- Synopsys Showcases NVIDIA Partnership Impact and Ecosystem Innovation at GTC 2026
Latest News
- JEDEC® Previews LPDDR6 Roadmap Expanding LPDDR into Data Centers and Processing-in-Memory
- Siemens collaborates with TSMC to advance AI for semiconductor design
- Crypto Quantique Unveils Latest Lightweight Cryptographic Primitives for Securing the Edge
- GUC Announces 3nm 12 Gbps HBM4 PHY and Controller
- Arasan acheives the Industry's First ASIL-D Certification for its CAN XL IP Core