Improv board holds five Jazz processors
Improv board holds five Jazz processors
By Patrick Mannion , EE Times
February 5, 2001 (5:31 a.m. EST)
URL: http://www.eetimes.com/story/OEG20010202S0031
MANHASSET, N.Y. Improv Systems Inc. (San Jose, Calif.), a licensor of intellectual property for configurable DSP platforms, has announced a five-processor silicon implementation of its configurable Jazz Processor architecture. Called the Quintet, the silicon is available for evaluation in the Jazz Quintet Rehearsal Board, which delivers up to 1,400 million operations per second (Mops) at 100 MHz, Improv said. The processor is comprised of a control section, data memory modules and a set of computation units. Each 32-bit, fixed-point Jazz processor is based on a VLIW architecture and has a built-in multiprocessor capability. The processors are built in a 0.2-micron, five-layer metal CMOS process by Philips Semiconductors, and each consumes 2.75 W. The performance of each processor ranges from 700 to 1,400 Mops. The Jazz Quintet Rehearsal Board includes a PCI interface to download application software on a standard Windows NT PC. It also f eatures a predefined external bus interface to allow users to connect external devices or other resources directly to the Jazz Quintet device, enabling full or partial emulation of a target system. The board has been integrated into Improv's Jazz development environment, which allows users to specify that code execute on Jazz Quintet silicon rather than the internal simulator in the Jazz IDE. The board is supported with a high-level language compiler that generates code for all five processors from a single source code file. The five-processor implementation is targeted at advanced applications such as wired and wireless communications, and audio and video processing. The Jazz Quintet Rehearsal Board can also be used in conjunction with the company's recently announced Acappela solution for voice-over-packet applications to execute speech codecs, echo cancellation and related voice-over-IP algorithms, the company said.
Related Semiconductor IP
- ISO/IEC 7816 Verification IP
- 50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL
- Simulation VIP for AMBA CHI-C2C
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
Related News
- Improv moves Jazz DSP core into high-volume 16-bit markets
- Improv Systems's Jazz DSPs linked to ARM; Hynix taps Virtual Silicon
- Improv launches first application platform using its Jazz processor
- Improv's Jazz DSP Tops EEMBC's Telecom Benchmark
Latest News
- Quintauris and Andes Technology Partner to Scale RISC-V Ecosystem
- Europe Achieves a Key Milestone with the Europe’s First Out-of-Order RISC-V Processor chip, with the eProcessor Project
- Intel Unveils Panther Lake Architecture: First AI PC Platform Built on 18A
- TSMC September 2025 Revenue Report
- Andes Technology Hosts First-Ever RISC-V CON in Munich, Powering Next-Gen AI and Automotive Solutions