Gaisler Research and Aldec partner to increase IP core availability and portability
February 21, 2007 -- Gaisler Research, a leading provider of IP core solutions from Gothenburg, Sweden, announced it has partnered with Aldec Inc., Henderson, USA, a pioneer in mixed language verification and advanced debugging tools for FPGA and ASIC devices.
The GRLIB IP core library from Gaisler Research is ideally suited for SoC designs and implements plug and play capabilities that minimize the engineering effort during the design phase. It includes the widely popular LEON3 user-customizable 32-bit SPARC V8 processor. The partnership will ensure that Aldec’s Active-HDL and Riviera simulator users can readily download and simulate a large set of very advanced and mature IP cores.
“We are pleased to be working with Aldec and look forward to a successful partnership to increase the number of IP cores that are supported by their simulator tools, and at the same time ensure that our IP cores are truly portable between design environments” stated Per Danielsson, CEO of Gaisler Research.
“Aldec and Gaisler Research engineering teams are working together to ensure that the GRLIB IP core library is compatible with the Active-HDL and Riviera mixed language simulators. The latest GRLIB release already includes support for these tools on Windows and Linux platforms” added Sandi Habinc, Senior Vice President of Engineering, Gaisler Research.
“Gaisler Research has been constantly delivering advanced and demanding IP cores, our cooperation will ensure compatibility while our tools evolve and their cores become more complex”," stated David Rinehart, Vice President of Aldec, Inc.
Availability
The GRLIB IP core library with Active-HDL and Riviera support is available today and can be downloaded from Gaisler Research's website. The library is supported by Aldec's software solutions operating on Windows and Linux platforms. The GRLIB IP core library is sold and supported by Gaisler Research and its distributors, while Active-HDL and Riviera are sold and supported by Aldec, Inc and its distributors.
About Aldec
Aldec, Inc., a 22-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux and Windows platforms. Aldec is dedicated and responsive to serving its customers’ needs. It is recognized that to be productive in today’s market and to best serve customers in the future, new technologies and innovations that go beyond traditional methods of conducting business in the EDA industry must be pursued. Aldec is committed to customer service and is actively developing a company that will evolve along with its customers' designs. Additional information about Aldec is available at http://www.aldec.com.
About Gaisler Research AB
Gaisler Research AB is a provider of SoC solutions for exceptionally competitive markets such as Aerospace, Military and demanding Commercial applications. Gaisler Research's products consist of user-customizable 32-bit SPARC V8 processor cores, peripheral IP-cores and associated software and development tools. Gaisler Research solutions help companies develop highly competitive customer and application-specific SoC designs.
The GRLIB IP core library from Gaisler Research is ideally suited for SoC designs and implements plug and play capabilities that minimize the engineering effort during the design phase. It includes the widely popular LEON3 user-customizable 32-bit SPARC V8 processor. The partnership will ensure that Aldec’s Active-HDL and Riviera simulator users can readily download and simulate a large set of very advanced and mature IP cores.
“We are pleased to be working with Aldec and look forward to a successful partnership to increase the number of IP cores that are supported by their simulator tools, and at the same time ensure that our IP cores are truly portable between design environments” stated Per Danielsson, CEO of Gaisler Research.
“Aldec and Gaisler Research engineering teams are working together to ensure that the GRLIB IP core library is compatible with the Active-HDL and Riviera mixed language simulators. The latest GRLIB release already includes support for these tools on Windows and Linux platforms” added Sandi Habinc, Senior Vice President of Engineering, Gaisler Research.
“Gaisler Research has been constantly delivering advanced and demanding IP cores, our cooperation will ensure compatibility while our tools evolve and their cores become more complex”," stated David Rinehart, Vice President of Aldec, Inc.
Availability
The GRLIB IP core library with Active-HDL and Riviera support is available today and can be downloaded from Gaisler Research's website. The library is supported by Aldec's software solutions operating on Windows and Linux platforms. The GRLIB IP core library is sold and supported by Gaisler Research and its distributors, while Active-HDL and Riviera are sold and supported by Aldec, Inc and its distributors.
About Aldec
Aldec, Inc., a 22-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux and Windows platforms. Aldec is dedicated and responsive to serving its customers’ needs. It is recognized that to be productive in today’s market and to best serve customers in the future, new technologies and innovations that go beyond traditional methods of conducting business in the EDA industry must be pursued. Aldec is committed to customer service and is actively developing a company that will evolve along with its customers' designs. Additional information about Aldec is available at http://www.aldec.com.
About Gaisler Research AB
Gaisler Research AB is a provider of SoC solutions for exceptionally competitive markets such as Aerospace, Military and demanding Commercial applications. Gaisler Research's products consist of user-customizable 32-bit SPARC V8 processor cores, peripheral IP-cores and associated software and development tools. Gaisler Research solutions help companies develop highly competitive customer and application-specific SoC designs.
Related Semiconductor IP
- HBM4 PHY IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
- VIP for Compute Express Link (CXL)
- HBM4 Controller IP
Related News
- Cobham Gaisler successfully verifies its first RISC-V processor, NOEL-V, using Aldec's Riviera-PRO for HDL Simulation
- GPU shipments increase year-over-year in Q3
- Fraunhofer IPMS remains important research partner for GlobalFoundries Dresden
- Lossless Data Compression Webinar: Choosing Algorithms and IP Core Accelerators
Latest News
- Tenstorrent unveiled its first-generation compact AI accelerator device designed in partnership with Razer™ today at CES 2026
- Marvell to Acquire XConn Technologies, Expanding Leadership in AI Data Center Connectivity
- Creonic Releases Updated SDA OCT IP Core Supporting OCT 4.0 and Enhanced Synchronization
- Synopsys Showcases Vision For AI-Driven, Software-Defined Automotive Engineering at CES 2026
- Ceva Delivers Real-Time AI Acceleration on NXP’s Processors for Software-Defined Vehicles