Fujitsu Kansai-Chubu Net-Tech Shortens Design Time by 40 Percent on 100G Transport System with Cadence High-Level Synthesis Solution

SAN JOSE, Calif. -- Dec 17, 2014 -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Fujitsu Kansai-Chubu Net-Tech Limited (KCN) utilized the Cadence® C-to-Silicon Compiler to shorten turnaround time by 40 percent compared to its traditional RTL process for a complex 100G transport system design.

KCN used the SystemC-based design approach for the transport system pipelines, reducing code size by more than half, and used the C-to-Silicon Compiler high-level synthesis for quick iterations to tune the functional specification and generate the optimized RTL implementation. By changing the design constraints to the C-to-Silicon Compiler, KCN was able to explore different micro-architectures and significantly reduced the place-and-route turnaround time. Fixing a place-and-route issue with traditional RTL design at Fujitsu took three days, but only half a day with the C-to-Silicon Compiler.

“Our highly integrated 100Gbps transport systems operate at very high frequency, which presented a major design challenge,” said Mr. Masao Nakano, design engineer, Device Development Department, Network Products Division, Fujitsu Kansai-Chubu Net-Tech. “By designing at a higher level of abstraction in SystemC, our design team was able to implement the customized hardware much more quickly and effectively."

For more information on the Cadence C-to-Silicon Compiler, visit www.cadence.com/news/c2s.

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