FinFETs Flow at Samsung, TSMC
Apple, Qualcomm are key customers
Jessica Lipsky, EETimes
2/3/2016 10:00 AM EST
SAN DIEGO, Calif. – Production of next-generation FinFET chips is underway at Samsung and TSMC. Although Samsung announced mass production of its 14nm LPP process technology with a major customer win in Qualcomm, TSMC may have the last laugh with Apple using its process.
In January, Samsung announced its 14nm Low Power Plus (LPP) process with 14% more performance than its LPE process, 0.8V power profile, and a 10% smaller die size over 28nm. Qualcomm will build its Snapdragon 820 chips in 14nm LPP, and Globalfoundries has licensed the process for its fabs.
“This is a great endorsement by a tier one company,” said Samsung Semiconductor's Kelvin Low, senior director of foundry marketing. “Especially many years ago when we started foundry business, there was always a concern about Samsung competing with our customers.”
To read the full article, click here
Related Semiconductor IP
- USB 20Gbps Device Controller
- Fault Tolerant DDR2/DDR3/DDR4 Memory controller
- 25MHz to 4.0GHz Fractional-N RC PLL Synthesizer on TSMC 3nm N3P
- AGILEX 7 R-Tile Gen5 NVMe Host IP
- 100G PAM4 Serdes PHY - 14nm
Related News
- Silicon Creations Taps Silvaco's Custom Design Flow for 10nm FinFET Designs
- Silicon Creations Relies on Silvaco's Custom Design Flow for New Advanced FinFET Designs
- Synopsys Full EDA Flow First to Achieve Samsung Foundry 4LPP Process Certification
- Synopsys 3DIC Compiler Qualified for Samsung Foundry's Multi-Die Integration Flow, Accelerating 2.5D and 3D Designs
Latest News
- Qualitas Semiconductor Successfully Demonstrates Live UCIe PHY IP at AI Infra Summit 2025
- Silicon Creations Announces 1000th Production FinFET Tapeout at TSMC and Immediate Availability of Full IP Library on TSMC N2 Technology
- Intel and NVIDIA to Jointly Develop AI Infrastructure and Personal Computing Products
- Comcores MACsec IP is compliant with the OPEN Alliance Standard
- Sofics joins GlobalFoundries’ GlobalSolutions Ecosystem to Enhance Chip Robustness, Performance and Design Efficiency