ESL needs more work, panelists say
(02/09/2006 2:11 PM EST)
SANTA CLARA, Calif. — Electronic system level (ESL) design tools and methodologies have value, but many capabilities have yet to be developed, according to users and vendor representatives at a panel at the DesignCon 2006 conference here Wednesday (Feb. 8).
The panel was entitled "The bottom-line business impact of ESL: getting the right architecture right." Moderator Daya Nadamuni, analyst at Gartner Dataquest, described three ESL design methodologies identified by Dataquest — algorithmic, processor/memory, and control logic.
Jack Donovan, co-founder of training firm ESLX, said that customers are looking for requirements traceability, early software development, reuse of verification models, and behavioral synthesis.
To read the full article, click here
Related Semiconductor IP
- Root of Trust (RoT)
- Fixed Point Doppler Channel IP core
- Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)
- Polyphase Video Scaler
- Compact, low-power, 8bit ADC on GF 22nm FDX
Related News
- ESL may rescue EDA, analysts say
- Platform ASICs a natural fit at 90 nm, say DAC panelists
- Software limits multi-core ICs, panelists say
- Startups say ESL adoption accelerating
Latest News
- BrainChip Provides Low-Power Neuromorphic Processing for Quantum Ventura’s Cyberthreat Intelligence Tool
- Ultra Accelerator Link Consortium (UALink) Welcomes Alibaba, Apple and Synopsys to Board of Directors
- CAST to Enter the Post-Quantum Cryptography Era with New KiviPQC-KEM IP Core
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology
- Arm Announces Appointment of Eric Hayes as Executive Vice President, Operations