ESL needs more work, panelists say
(02/09/2006 2:11 PM EST)
SANTA CLARA, Calif. — Electronic system level (ESL) design tools and methodologies have value, but many capabilities have yet to be developed, according to users and vendor representatives at a panel at the DesignCon 2006 conference here Wednesday (Feb. 8).
The panel was entitled "The bottom-line business impact of ESL: getting the right architecture right." Moderator Daya Nadamuni, analyst at Gartner Dataquest, described three ESL design methodologies identified by Dataquest — algorithmic, processor/memory, and control logic.
Jack Donovan, co-founder of training firm ESLX, said that customers are looking for requirements traceability, early software development, reuse of verification models, and behavioral synthesis.
To read the full article, click here
Related Semiconductor IP
- xSPI Multiple Bus Memory Controller
- MIPI CSI-2 IP
- PCIe Gen 7 Verification IP
- WIFI 2.4G/5G Low Power Wakeup Radio IP
- Radar IP
Related News
- ESL may rescue EDA, analysts say
- Platform ASICs a natural fit at 90 nm, say DAC panelists
- Software limits multi-core ICs, panelists say
- Startups say ESL adoption accelerating
Latest News
- Premier ASIC and SoC Design Partner, Sondrel, Rebrands as Aion Silicon
- Intel Financial Risks, Layoffs, Foundry Ambitions
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
- China Takes the Lead in RF Front-End Patent Activity: RadRock and Others Surge Behind Murata
- Arteris Wins Two Gold and One Silver Stevie® Awards in the 2025 American Business Awards®