Platform ASICs a natural fit at 90 nm, say DAC panelists

Nicolas Mokhoff
(06/17/2005 9:47 AM EDT)

  ANAHEIM, Calif. — Panelists debating the merits of platform ASICs agreed designers are entering an era of more uncertainty at the 90-nm process node than at any other technology shift.

During a panel discussion at the Design Automation Conference here Thursday (June 16), panelists noted that Moore's law delivers higher performance and lower cost for both FPGAs and ASICs. But at the 90-nm process node and below, platform ASICs or FPGAs are emerging as an alternative design platform.

Chris Hamlin, senior vice president and chief technology officer of LSI Logic Corp. (Milpitas, Calif.), said that Moore's Law has a corollary called compound complexity. "This, coupled with escalating fixed design costs, is forcing reconsideration of some basic assumptions," said Hamlin.

For ASICs this means new formal approaches to architecture and abstraction will eventually redefine what it means to design a high complexity device. "We are rapidly approaching the time when designers will take the well-defined platform ASIC with its foundation of dedicated metal levels and apply that same structure to the architectures suitable for a number of applications," added Hamlin.

Steve Leibson, strategic marketing manager at Tensilica (Santa Clara, Calif.), said "Rising chip complexity has once again forced design teams to move up a level of abstraction. We need automated ways of transforming high-level system and algorithmic descriptions into hardware."

Leibson was advocating a high-level abstraction design methodology that is feasible across FPGAs, structured ASICs, standard-cell ASICs, and custom ASSPs. "Most of the designs stuck at the RTL need to move up to algorithmic modeling."

Raul Camposano, senior vice president, chief technology officer, and general manager of the Silicon Engineering Group at Synopsys Inc. (Mountain View, Calif.), discussed how ASICs are evolving to meet changing design needs. "ASICs and ASSPs have been a formidable economic force, accounting for over one third of the semiconductor market," he said."

But the cost of ASIC respins and the increasing time to market have prompted the search for other design styles, said Camposano. These include structured ASICs, FPGAs, processor arrays and "platforms which are not replacing ASIC designs but rather are reviving cell-based design by adding flexibility to traditional ASIC design in the form of embedded programmable blocks."

Both structured ASICs and platform ASICs hide the problems of working with them in different ways, said Ken McElvain, chief technical officer at Synplicity Inc. (Sunnyvale, Calif.). "Platform ASICs offer more advantages to smaller companies to get designs done cost-efficiently," he added.

Ivo Bolson, vice president and chief technical officer of Xilinx Inc. (San Jose, Calif.), claimed that due to the challenges imposed by designing and manufacturing deep submicron chips, today, people would have to invent FPGAs if they didn't already exist. "Alternative approaches such as structured ASICs are introducing many new problems ranging from inventory management to tool support," said Bolson.

Michele Borgatti, front-end technology and manufacturing manager at STMicroelectronics (Geneva, Switzerland), claimed that platform ASICS will be the highest volume in the consumer electronics era. "The economics favor platform ASICs because they can span a lot more applications using well defined cells augmented by designed cells for each application," said Borgatti.