eDisplay Port/Display Port v1.4 Tx PHY and Controller IP Cores in 12FFC and 40LP for cutting edge display applications is available for immediate licensing

10^th January 2022 – T2M^IP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s VESA standard eDisplay Port/Display Port v1.4 Tx Controller and matching PHY IP Cores in 40nm LP and 12nm FFC which are silicon proven in major Fabs capable of 8K and 4K resolutions.

eDisplayPort/ DisplayPort 1.4 Tx Controller IP Cores version 1.4 compliant transmitter supports Embedded DisplayPort (eDP) which is a display panel interface standard for portable and embedded devices. It defines the signaling interface between graphics cards and integrated displays. This IP core consists of configurable (4/2/1) link channels and one AUX channel that makes it flexible for use with added benefit of backward compatibility. It also supports 1.62/2.7/5.4/8.1Gbps (HBR3) bit rate and all recommended link rate. The Transmitter Controller core supports main link operation with 1 or 2 or 4 lanes, which can in turn facilitate support for Default and Enhanced Framing Mode, SST mode, Normal and Alternate Scrambler Seed Reset.

This DisplayPort 1.4 Tx PHY IP Core enables Ultra High Definition (UHD) and High Dynamic Range (HDR) display with support for 1.62Gbps (RBR) to 8.1Gbps (HBR3) bit rate. Equipped with configurable analog characteristics such as integrated 100-ohm termination resistors with common-mode biasing and Integrated equalizer with tuneable strength, at about 1.8V/0.9V power supply makes it powerful, yet less energy consuming. eDisplay Port / Display Port v1.4 Tx PHY IP Cores packetized data transmission allows higher resolution using fewer pins. Along with supports for HDCP 2.2, HDCP 1.4 and with Display Stream Compression 1.2 (DSC), Forward Error Correction’s bandwidth reduction, the DisplayPort 1.4 standard can be used to transport video streams across a single DisplayPort interface for high end display applications with 8K and 4K resolutions with a clear lossless video compression technology that multiplies the DisplayPort data transfer capacity

The eDisplayPort/DisplayPort v1.4 Tx Controller IP Cores comes with Verilog RTL or netlist source code of LINK controller and Simulation testbench. The eDisplayPort/DisplayPort v1.4 Tx PHY IP Core is also available in process nodes other than 40 LP and 12 FFC in major Fabs, which are proven and in production chips such as computing, digital displays, monitors, TVs and other consumer electronics.

In addition to Display Port/eDisplayPort IP Cores, T2M‘s broad silicon Interface IP Core Portfolio includes USB, HDMI, MIPI (CSI, DSI, UniPro, UFS, Soundwire, I3C), PCIe, DDR, 10/100/1000 Ethernet, V by One, programmable SerDes, Serial ATA and many more, available in major Fabs in process geometries as small as 7nm. They can also be ported to other foundries and leading-edge processes nodes on request.

Availability:

These Semiconductor Interface IP Cores are available for immediate licensing either stand alone or with pre-integrated Controllers and PHYs. For more information on licensing options and pricing please drop a request / MailTo

About T2M:

T2M^IP is the global independent semiconductor technology experts, supplying complex semiconductor IP Cores, Software, KGD and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB and Satellite SoCs. For more information, please visit: www.t-2-m.com