EDA, AVs Find Common Language
By Junko Yoshida, EEtimes
August 12, 2019
Complex systems — whether a system-on-chip or autonomous vehicles — can frustrate design engineers who, after months of painstaking work, have to go back and verify that the system they just designed actually performs the way they intended.
SoCs and autonomous vehicles (AVs) are both built in a “black box,” which by nature makes it hard to find bugs “hiding in places that you don’t think about,” said Ziv Binyamini, CEO and co-founder of a Tel Aviv-based startup called Foretellix.
In testing and verifying an SoC, two measures are deemed essential: “code coverage,” which tells how well the code is tested by stimulus, and “functional coverage,” a way for the user to write certain instrumentation logic that monitor how well the stimulus is covering various functions.
Foretellix believes that similar coverage-driven disciplines should apply to AVs when car OEMs test safety.
To read the full article, click here
Related Semiconductor IP
- HiFi iQ DSP
- CXL 4 Verification IP
- JESD204E Controller IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
Related News
- STARC Selects Verisity's e Verification Language for IP Reuse <!-- verification --> --> "Arial,Helvetica" size=-1 > Headline News
- Engineer offers open-source verification language <!-- verification -->
- Industry Support Builds for Intel"s Formal Property Verification Language Initiative
- Intel pushes assertion language as EDA standard <!-- verification -->
Latest News
- A new CEO, a cleared deck: Is Imagination finally ready for a deal?
- SkyeChip’s UCIe 3.0 Advanced Package PHY IP for SF4X Listed on Samsung Foundry CONNECT
- Victor Peng Joins Rambus Board of Directors
- Arteris Announces Financial Results for the Fourth Quarter and Full Year 2025 and Estimated First Quarter and Full Year 2026 Guidance
- Arteris Network-on-Chip Technology Achieves Deployment Milestone of 4 Billion Chips and Chiplets