EDA, AVs Find Common Language
By Junko Yoshida, EEtimes
August 12, 2019
Complex systems — whether a system-on-chip or autonomous vehicles — can frustrate design engineers who, after months of painstaking work, have to go back and verify that the system they just designed actually performs the way they intended.
SoCs and autonomous vehicles (AVs) are both built in a “black box,” which by nature makes it hard to find bugs “hiding in places that you don’t think about,” said Ziv Binyamini, CEO and co-founder of a Tel Aviv-based startup called Foretellix.
In testing and verifying an SoC, two measures are deemed essential: “code coverage,” which tells how well the code is tested by stimulus, and “functional coverage,” a way for the user to write certain instrumentation logic that monitor how well the stimulus is covering various functions.
Foretellix believes that similar coverage-driven disciplines should apply to AVs when car OEMs test safety.
To read the full article, click here
Related Semiconductor IP
- Bluetooth Low Energy 6.0 Digital IP
- Ultra-low power high dynamic range image sensor
- Flash Memory LDPC Decoder IP Core
- SLM Signal Integrity Monitor
- Digital PUF IP
Related News
- STARC Selects Verisity's e Verification Language for IP Reuse <!-- verification --> --> "Arial,Helvetica" size=-1 > Headline News
- Engineer offers open-source verification language <!-- verification -->
- Industry Support Builds for Intel"s Formal Property Verification Language Initiative
- Intel pushes assertion language as EDA standard <!-- verification -->
Latest News
- Intel facing another crossroads: 18A or 14A process node
- Creonic Successfully Renewed its ISO 9001:2015 Certification
- Silvaco Strengthens Leadership Team with Three Industry Veterans to Drive Innovation and Growth
- JFE Shoji Electronics Signs Sales Agent Agreement with Andes Technology
- Mixel Supports Automotive SerDes Alliance (ASA) Motion Link SerDes IP