DesignCon 2019: eSilicon to demonstrate 7nm 56G DSP SerDes over 5-meter Samtec cable assembly
January 23, 2019 -- eSilicon, a leading provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, will team up with Samtec to demonstrate eSilicon’s 7nm 56G full-DSP SerDes over Samtec’s 5m ExaMAX® Backplane Cable Assembly.
eSilicon will also participate in Test Fixture Signal Integrity for 112G PAM-4: Lively Panel Discussion on the Top Design Rules.
SerDes Demonstrations: Samtec Booth 737
Wednesday-Thursday
January 30-31, 2019
Using Samtec ExaMAX Backplane Connector paddle cards and a 5m ExaMAX Backplane Cable Assembly, eSilicon will demonstrate the performance, flexibility and extremely low power consumption of its 7nm, 56G PAM4 and NRZ DSP-based long-reach SerDes.
Forward error correction (FEC)-free operation will be showcased across multiple channels, operation frequencies and modulation schemes, thanks to a very powerful and programmable real-time DSP-based equalization capability. Bit-error rate, eye diagram monitors and pulse response processing will be shown among many other capabilities.
Panel Discussion:
Test Fixture Signal Integrity for 112G PAM-4: Lively Panel Discussion on the Top Design Rules
Wednesday, January 30
10:00-10:45 AM
Panelists: Tim Horel, eSilicon; Scott McMorrow, Samtec; Al Neves, Wild River; Heidi Barnes, Keysight; Jason Ellison, Amphenol.
About DesignCon
January 29-31, 2019
Santa Clara convention Center
Santa Clara, Calif.
As the nation’s largest event for chip, board, and systems designers, DesignCon is a must-attend opportunity to share ideas, overcome challenges, and source solutions.
About eSilicon
eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Our neuASIC™ platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, artificial intelligence (AI) and 5G infrastructure markets. www.esilicon.com
Related Semiconductor IP
- Real-Time-Clock Analog, Include 32K XOSC, Capaless LDO, POR, VDT - TSMC 7nm
- 24-Bit Stereo Audio Codec ADC, ADC SNR>95dB, DAC SNR>100dB - TSMC 7nm
- 12-Bit 2MSPS SAR ADC, 10.5 Bit ENOB - TSMC 7nm
- 1-56Gbps Serdes - 7nm (Multi-reference Clock)
- 1-56Gbps Serdes - 7nm (Ultra Low Latency)
Related News
- OFC 2019: eSilicon to demonstrate two 7nm IP products, 56G DSP SerDes over a 5-meter Samtec cable assembly and a complete HBM2 PHY subsystem
- OCP 2019: eSilicon to demonstrate 56G DSP SerDes over a 5-meter cable assembly in Samtec booth
- ISSCC 2019: eSilicon to present a paper and demonstrate 7nm 56G DSP SerDes operation over a five-meter cable assembly
- Linley Spring Processor Conference 2019: eSilicon to demonstrate 7nm DSP SerDes over a 5-meter cable assembly and present on IP platforms
Latest News
- Jim Keller: ‘Whatever Nvidia Does, We’ll Do The Opposite’
- FlexGen Streamlines NoC Design as AI Demands Grow
- IntoPIX Presents Its New Titanium Software Suite: Empowering AV-Over-IP Workflows With Speed, Quality & Interoperability
- Global Semiconductor Sales Increase 2.5% Month-to-Month in April
- Speedata Raises $44M to Launch First-Ever Chip Designed Specifically for Accelerating Big Data Analytics - Compute's Second Largest Workload