Design Verification Challenges in Modern SoCs - HDL Design House Webinar

Igor Ikodinovic, HDL Design House’s Principal Project Manager will host an online event about various issues that arise in today’s SoC design verification and how to solve them efficiently and effectively.

Belgrade, Serbia – May 31^st, 2016 – HDL Design House, provider of digital, analog, and back-end design and verification services and products in numerous areas of SoC, will host a webinar to be presented by Mr Igor Ikodinovic, Principal Project Manager, who will discuss how different standard as well as numerous non-standard verification challenges are dealt with in practice by HDL Design House.

Modern SoCs contain a large number of digital and analog modules whose functionality needs to be verified at the system (top) level. A number of different problems arise in this process, including how to choose the verification methodology, language and implementation platform, how to create proper test plans, how to ensure functional coverage conversion, how to perform verification using different power modes, and more.

Beside these standard verification problems, the list often includes non-standard problems such as how to properly model analog modules in the SoC verification environment, how to model system performance and verify that system performance goals are met, improving the workflow or tools used, and others. The webinar will outline a practical approach to resolving these issues.

This online event will include topics such as advantages of coverage-driven constrained-random verification methodology, UVM-based SoC functional verification flow, creating test plans and ensuring coverage conversion, challenges of SoC performance verification, and verification of analog blocks in SoC design verification environment.

The webinar is taking place on Thursday 16 June, 10 am PST and is free to attend. Joining instructions are available on the webinar registration page on HDL Design House website:

https://www.hdl-dh.com/webinar.html

About HDL Design House:

HDL Design House delivers leading-edge digital, analog, and back-end design and verification services and products in numerous areas of SoC and complex FPGA designs. The company also develops IP cores, developed and verified using Cadence tools and flow, and component (VITAL) models for major SoC product developers. Founded in 2001 and currently employing 140 engineers working in three design centers in Serbia and Greece, HDL Design House’s mission is to deliver high quality products and services, with flexible licensing models, competitive pricing and responsible technical support. The company was awarded ISO 9001:2008 and ISO 27001:2013 certifications in December 2006 and has achieved certifications from Direct Assessment Services (DAS). For more information, please visit www.hdl-dh.com