Commentary: Developers Look Set to increase FPGA IP Costs
By Richard Wilson -- 4/1/2004
Electronics Weekly
Electronics Weekly
The cost of designing specialist intellectual property into FPGAs may have to increase as independent IP developers look at ways to lift margins.
The implication is that it could increase the up-front engineering cost of designing an FPGA.
"The FPGA industry is starting to hit some ASIC-like cost issues," said Alan Matthews, European marketing director at Xilinx.
Read more ....
Related Semiconductor IP
- USB 20Gbps Device Controller
- 25MHz to 4.0GHz Fractional-N RC PLL Synthesizer on TSMC 3nm N3P
- AGILEX 7 R-Tile Gen5 NVMe Host IP
- 100G PAM4 Serdes PHY - 14nm
- Bluetooth Low Energy Subsystem IP
Related News
- Commentary: More chip makers going 'fabless' to lower costs
- New eSilicon Direct Model Lowers Risks and Costs for Custom Chip Developers
- Commentary: Lower test costs start with IC design
- Dolphin Design chooses DEFACTO's SoC Compiler 9.0: a turnkey methodology to reduce project costs and increase team efficiency
Latest News
- 2025 TSMC OIP Ecosystem Forum Highlights Aion Silicon’s Leadership in Advanced SoC Design
- Ceva Appoints Former Microsoft AI and Hardware Leader Yaron Galitzky to Accelerate Ceva’s AI Strategy and Innovation at the Smart Edge
- Dnotitia Unveils VDPU IP, the First Accelerator IP for Vector Database
- Ambient Scientific AI-native processor for edge applications offers 100x power and performance improvements over 32-bit MCUs
- Qualitas Semiconductor Signs PCIe Gen 4.0 PHY IP License Agreement with Leading Chinese Fabless Customer