Codasip Announces a New Design Center in France
Munich, Germany – October 20th, 2020 – Codasip, the leading supplier of customizable RISC-V embedded processor IP, announced its new strategic design center today. It is based in France and the local Codasip team is going to play an important role in the company’s innovation and development plans for the next-generation product IP.
The new Codasip French Design Center started operation in the summer. It is located in Villeneuve Loubet on the Mediterranean coastline in southeast France, near the technology park of Sophia Antipolis where major technology companies such as Bosch, NXP, Thales, and many others have offices.
“As we are expanding the product portfolio and fostering our technology leadership, we need talented senior engineers to support the growth,” explained Karel Masařík, CEO of Codasip. “Sophia Antipolis is an important European location for R&D and technical talent in the semiconductor industry. We are proud to have hired our French colleagues there, close to customers. Their expertise will be a great supplement to that of our main R&D Center in the Czech Republic.”
The newly established Codasip French team is currently focused mainly on product architecture and verification. The team’s leader is Mélaine Facon, an industry professional with rich experience in the semiconductor IP design field.
“The RISC-V open ISA is revolutionizing the deployment of processors in SoCs by being a neutral standard independent of any single company,” said Mélaine Facon, Director of the French Design Center. “We are confident that our team’s experience can help respond to the rapidly increasing demand for RISC-V processors, and we are really looking forward to becoming a part of Codasip and its RISC-V story.”
The full address of the Codasip French Design Center is available on the Codasip website, section Contact.
About Codasip
Codasip delivers leading-edge processor IP and high-level processor design tools, providing ASIC designers with all the advantages of the RISC-V open ISA, along with the unique ability to automatically optimize the processor IP. As founding member of the RISC-V Foundation and a long-time supplier of LLVM and GNU‑based processor solutions, Codasip is committed to open standards for embedded processors. Formed in 2014 and headquartered in Munich, Germany, Codasip currently has offices in Europe and China, with sales representatives worldwide. For more information about our products and services, please visit www.codasip.com.
Related Semiconductor IP
- RISC-V Debug & Trace IP
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- Compact Embedded RISC-V Processor
- Multi-core capable 64-bit RISC-V CPU with vector extensions
- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
Related News
- Safe and Secure Technologies, the new BSC and UPC spin-off that will design chips for critical sectors where “failure is not an option”
- Codasip Opens UK Design Center led by Simon Bewick
- Thalia enhances AMALIA Platform with new AI models to revolutionize analog, RF and mixed-signal IC design migration
- StarIC opens design center in The Netherlands
Latest News
- Seligman Ventures Leads Cognichip’s $60M Series A to Back Physics-Informed AI for Chip Design, Intel CEO Lip-Bu Tan and Seligman Ventures’ Umesh Padval Join the Board
- SEMI Projects Double-Digit Growth in Global 300mm Fab Equipment Spending for 2026 and 2027
- Intel to Repurchase 49% Equity Interest in Ireland Fab Joint Venture
- AGI CPU: Arm’s $100B AI Silicon Tightrope Walk Without Undermining Its Licensees
- EnSilica selected for UK CHERI Adoption Collective