ClariPhy Licenses Tensilica's Xtensa Dataplane Processor (DPU) for Optical Networking Mixed Signal, Digital Signal Processing (MXSP) SOCs
Santa Clara, CA USA - March 1, 2012 - Tensilica, Inc. today announced that ClariPhy Communications, Inc., a leading developer of ultra-high speed mixed signal, digital signal processing (MXSP) system-on-chip (SOC) solutions for coherent optical networks, has licensed Tensilica's Xtensa dataplane processor unit (DPU) for a deeply embedded control application.
"We benchmarked other CPU and controller cores and selected Tensilica's Xtensa DPU because it offered us a unique combination of a robust standard architecture with a rich third party ecosystem, plus the ability to configure and extend the core to meet our exact applications need," stated Reza Norouzian, vice president of sales and business development at ClariPhy. "With Tensilica, we are able to leverage the reuse advantages while still reaping the benefits of differentiation arising from customization of the core."
"ClariPhy is aggressively pushing both high-performance and high-integration in optical networking infrastructure applications," stated Steve Roddy, Tensilica's vice president of marketing and business development. "As they strive for maximum performance at the lowest possible power, our automated processor core customization technology will help them reach their design goals."
About ClariPhy
ClariPhy Communications, Inc. develops mixed signal, advanced digital signal processing (MXSP) ICs targeting 10G, 40G, 100G and beyond for optical networks. ClariPhy's LightSpeed SoCs increase capacity and reach while eliminating costly regeneration equipment, simplifying network management and lowering system CAPEX and OPEX costs. ClariPhy's investors include Nokia Siemens Networks, Oclaro, Norwest Venture Partners, Onset Ventures, and Allegis Capital. ClariPhy is headquartered in Irvine, California with offices in Los Altos, California and Cordoba, Argentina. For more information, please visit http://www.clariphy.com.
About Tensilica
Tensilica, Inc. is the leader in dataplane processor IP cores. Dataplane processors (DPUs) are a superset of DSPs and CPUs that can scale from tiny micro signal processors to programmable offload accelerators and powerful DSPs. DPUs deliver 10 to 100x the performance because they can be optimized using Tensilica's automated design tools to meet specific and demanding signal processing performance and efficiency targets. Tensilica's DPUs power SOC designs at many Tier 1 system OEMs and seven out of the top 10 semiconductor companies for designs in mobile wireless, telecom and network infrastructure, computing and storage, and home and auto entertainment. For more information on Tensilica's patented, benchmark-proven DPUs visit www.tensilica.com.
Related Semiconductor IP
- 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
- 1.8V/3.3V I/O Library with ODIO and 5V HPD in TSMC 12nm
- 1.8V to 5V GPIO, 1.8V to 5V Analog in TSMC 180nm BCD
- 1.8V/3.3V GPIO Library with HDMI, Aanlog & LVDS Cells in TSMC 22nm
- Specialed 20V Analog I/O in TSMC 55nm
Related News
- Siemens' state-of-the-art Symphony Pro platform expands mixed signal IC verification capabilities
- Credo Introduces 800Gbps and 400Gbps Optical Digital Signal Processors with Integrated Drivers
- Cutting-edge 18-bit 100dB Stereo Audio ADC IP Core proven in 28nm Silicon, Offering Unmatched Audio Signal Processing Capabilities is available for immediate Licensing into Audio Chipsets, Digital Cameras, and Automotive Applications
- Actel Announces Power Management Solution for SmartFusion Intelligent Mixed Signal FPGAs
Latest News
- Will RISC-V reduce auto MCU’s future risk?
- Frontgrade Gaisler Launches New GRAIN Line and Wins SNSA Contract to Commercialize First Energy-Efficient Neuromorphic AI for Space Applications
- Continuous-Variable Quantum Key Distribution (CV-QKD) system demonstration
- Latest intoPIX JPEG XS Codec Powers FOR-A’s FA-1616 for Efficient IP Production at NAB 2025
- VeriSilicon Launches ISP9000: The Next-Generation AI-Embedded ISP for Intelligent Vision Applications