Cisco Rolls 16nm ASICs
Switch chips chop Broadcom Tomahawk
Rick Merritt
3/1/2016 01:00 PM EST
The new ASICs enable a more flexible set of interfaces for ports carrying 100Mbit to 100 Gbit/second Ethernet and 32 Gbit/s Fibre Channel traffic. The company claims the chips are the first to pack 36 100G ports in a system that fits in a single rack unit. The ASICs also implement flow control tables to monitor all traffic running across leaf and spine switches.
Cisco designed a family of three closely related ASICs for its systems with aggregate bandwidth ranging from 3.6 to 1.6 Terabits/second. Two of the chips, made in TSMC’s 16FF+ process, started shipping in systems in February, a third will ship within two months.
To read the full article, click here
Related Semiconductor IP
- HBM4 PHY IP
- eFuse Controller IP
- Secure Storage Solution for OTP IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
Related News
- Open-Silicon Tapes Out Industry's First High Bandwidth Memory (HBM2) IP Subsystem Solution for 2.5D ASICs in 16nm FF+
- Cyan rolls out 16-bit flash controller for embedded applications
- Mysticom shifts focus from IP to standard products, rolls out new DSP-based transceivers
- AMI Semi rolls out FPGA-conversion ASICs, uses TSMC as foundry in 'hybrid' fab strategy
Latest News
- LTSCT and Andes Technology Sign Strategic IP Licensing Master Agreement to accelerate RISC-V Based Advanced Semiconductor Solutions
- Global Semiconductor Sales Increase 29.8% Year-to-Year in November
- BAE Systems Licenses Time Sensitive Networking (TSN) Ethernet IP Cores from CAST
- HBM4 Mass Production Delayed to End of 1Q26 By Spec Upgrades and Nvidia Strategy Adjustments
- ASICLAND Secures USD 17.6 Million Storage Controller Mass Production Contract