Chipidea announces silicon validated analog IP cores in Chartered 0.18um CMOS Process
Porto Salvo, Portugal – February 23 2004
, ChipIdea Microelectrónica, S.A., a leading
analog and mixed-signal IP and SOC provider, has successfully validated in
Chartered 0.18um CMOS process a complete set of analog/mixed-signal IPs Cores
designed to cover a wide range of Analog Front-End requirements for wireless,
wireline and multi-media applications.
These IP Cores include:
- CI8225aa-10bit, 14MHz Current-Steering DAC
- CI8232aa-10bit 500kHz DAC
- CI7226aa- Audio 16 bit sigma-delta codec
- CI3227aa-8bit, 14MHz pipeline ADC
- CI3231aa-10bit, 100kHz SAR ADC
- CI2228aa-Power on reset with references
- CI2230aa-Distributed Voltage Regulator
- CI1229aa-240MHz clock multiplying PLL
- CI12233aa-USB2.0 LS/FS AFE
All above IPs show excellent performance in Silicon.
To see the whole report, please visit
http://www.chipidea.com/website_45c/ciflash/2004_2/flashnews19022004.html
Related Semiconductor IP
- NPU IP Core for Mobile
- NPU IP Core for Edge
- Specialized Video Processing NPU IP
- HYPERBUS™ Memory Controller
- AV1 Video Encoder IP
Related News
- ChipIdea's 210MHz Analog Interface for Flat Panel Displays Validated in Silicon at 0.18um TSMC
- Chipidea, Solid Silicon Technology Offer Integrated USB 2.0 and USB 2.0 OTG IP Solutions for Chartered's 0.13-Micron and 0.18-Micron Processes
- Chipidea Launches New Line of CMOS Radio Frequency IP Platforms
- Chipidea, Chartered Collaborate to Offer Advanced Mixed-Signal IP at 65nm
Latest News
- Jim Keller: ‘Whatever Nvidia Does, We’ll Do The Opposite’
- FlexGen Streamlines NoC Design as AI Demands Grow
- IntoPIX Presents Its New Titanium Software Suite: Empowering AV-Over-IP Workflows With Speed, Quality & Interoperability
- Global Semiconductor Sales Increase 2.5% Month-to-Month in April
- Speedata Raises $44M to Launch First-Ever Chip Designed Specifically for Accelerating Big Data Analytics - Compute's Second Largest Workload