Chinese start-up readies 64-bit processor
![]() |
Chinese start-up readies 64-bit processor
By Mike Clendenin, EE Times
March 7, 2003 (2:39 a.m. EST)
URL: http://www.eetimes.com/story/OEG20030305S0018
BEIJING Stay tuned: China's first homegrown CPU is about to go 64-bit. One of the country's most promising start-ups, BLX IC Design Corp., Ltd., told EE Times Wednesday (March 5) that it is closing in on a 500-MHz microprocessor that it will market toward China's leading server vendors, including Legend Group and Dawning Technology. It would eventually be positioned as the engine of a distributed grid computing network that will be used by public and private firms here. The chip is dubbed Godson-2 and is the follow-on to a 32-bit, 266-MHz version released last year that is aimed at the embedded systems market. Both chips are largely based on the MIPS instruction set, but are not fully compatible because they avoid the use of key instructions that would run afoul of MIPS patents. BLX has moved quickly to rally Chinese industry support around the architecture, launching an alliance that intends to attract 100 members and create 100 designs within two years. “We already have 60 companies and 15 designs so we are ahead of schedule,” said David Shen, chief executive of BLX. “We have started working with Haier, which is the biggest consumer manufacturer in China, and they need a lot of chips.” All of the 60 companies that have joined are Chinese firms, Shen said, and they range from upstream hardware makers, to consumer giants like Haier, and software providers Red Flag Linux and Great Wall Software Co. Godson-2, which has also been translated into English as Dragon or Longxin, has already been prototyped. Samples are expected to roll in the first half of next year. The chip will be binary backward compatible to the 32-bit Godson-1, a path of compatibility also chosen by Advanced Micro Devices in development of its Opteron line. Some of the improvements over Godson-1 include a four-issue super-scaler architecture, dynamic branch prediction and a non-blocking cache design to allow for multiple misses in the memory array. The chip will probably be made on a 0.18-micron process at Taiwan Semiconductor Manufacturing Co., although Shanghai's Semiconductor Manufacturing International Corp. is also being considered. Planning for Godson-3 Even though Godson-2 hasn't been officially rolled out, researchers at the Institute of Computing Technology (ICT), a government research group that first designed the Godson architecture before licensing it to BLX, are already thinking about a Godson-3. The core design will be similar. But more features should improve its standing. “By the end of next year, we hope we can add in multiprocessor support and on-chip secondary cache. If these features are added, the power consumption may be around 10 watts,” said Tang Zhimin, a senior ICT engineer who headed up the Godson project. The power budget for Godson-2 is around 5 watts, based on a 1.8V core and 3.3V I/O. Also under consideration are SIMD for multimedia proce ssing and multithreading support. “We are also looking at how to integrate multithreading with our current superscalar architecture,” Tang said.
Related Semiconductor IP
- 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
- 1.8V/3.3V I/O Library with ODIO and 5V HPD in TSMC 12nm
- 1.8V to 5V GPIO, 1.8V to 5V Analog in TSMC 180nm BCD
- 1.8V/3.3V GPIO Library with HDMI, Aanlog & LVDS Cells in TSMC 22nm
- Specialed 20V Analog I/O in TSMC 55nm
Related News
- MIPS Technologies and TSMC form strategic alliance to deliver "hard" versions of MIPS 32 and 64 Bit Processor Cores
- Intelop announces 10 G bit Ethernet MAC + PCIe + AMBA 2.0 Core which Receives and Transmits 64 - 1518 Byte packets at full line rate and is customizable for implementing differentiated application features
- Sydaap develops World’s First 64 Bit Floating Point FFT/IFFT Hardware Accelerator for N = 4096
- MIPS I6500-F First High Performance 64 Bit Multi-Cluster CPU IP to Receive ISO 26262 and LEC 61508 Certification
Latest News
- Will RISC-V reduce auto MCU’s future risk?
- Frontgrade Gaisler Launches New GRAIN Line and Wins SNSA Contract to Commercialize First Energy-Efficient Neuromorphic AI for Space Applications
- Continuous-Variable Quantum Key Distribution (CV-QKD) system demonstration
- Latest intoPIX JPEG XS Codec Powers FOR-A’s FA-1616 for Efficient IP Production at NAB 2025
- VeriSilicon Launches ISP9000: The Next-Generation AI-Embedded ISP for Intelligent Vision Applications