Atrenta to Demostrate Power of Predictive Analysis at DAC'02 in New Orleans
SpyGlass Products Predict Downstream Problems Early in Design Cycle
SAN JOSE, Ca. - June 3, 2002 - Atrenta Inc., the Predictive Analysis company, is offering integrated circuit designers a unique opportunity to see first hand why leading electronic and semiconductor companies are using its predictive analysis products BEFORE running simulation or synthesis. At this year’s Design Automation Conference (DAC), June 10-12, 2002 in New Orleans, Atrenta will demonstrate its SpyGlassä family of predictive analysis products. These products help predict and identify SoC (system-on-chip) integration issues, testability issues and RTL (register-transfer level) handover issues that normally only show up much later in the design process. By fixing these problems early, designers can significantly cut their SoC design time. Engineers can see Atrenta’s SpyGlass products in booth 2925 or sign up for an in-depth demonstration in suite 4006.
Atrenta will be highlighting three new products introduced earlier this year: SpyGlass SoC, SpyGlass DFT and SpyGlass 3.0. SpyGlass SoC enables design teams to carefully evaluate incoming IP (intellectual property) and internally designed RTL blocks to ensure it meets project guidelines. In addition to hookup checks, SpyGlass SoC zeroes in on tough issues that often cause significant delays in SoC integration, such as race conditions, clock synchronization, set/reset consistency and much more. This aligns all the blocks for quick integration and eliminates schedule delays caused by inconsistent design practices.
SpyGlass DFT focuses testability analysis at the RTL development stage, detecting problems and guiding designers to the best possible solutions. This proactive approach lets designers know, right from the start, if their design is scan ready and if the required fault coverage will be met. SpyGlass DFT pinpoints un-testable logic and suggests changes that let designs speed through the testing process.
SpyGlass 3.0 identifies complex design problems and downstream tool flow issues right up front at RTL creation time, resulting in early detection of problems, fewer design iterations and early time to market. RTL problems that cause handover issues, including timing and layout problems, are detected early in the design cycle. SpyGlass reports on logic depth between registers by source and destination clock domains, snake paths that may create floorplanning and timing issues, un-driven signals, and dead-code.
To sign up for an in-depth demonstration at Atrenta’s suite, designers should email dac@atrenta.com.
About Atrenta
Atrenta offers a new approach in accelerating the design of complex
ASICs, FPGAs, and SoCs through predictive analysis. Its SpyGlass software
is the first tool that performs detailed structural analysis on register-transfer-level
Verilog and VHDL code in order to check for complex problems, which include
coding styles, RTL-handoff, design re-use, clock/reset requirements, and
much more. Its breakthrough and innovative “look-ahead” capability incorporates
a fast-synthesis engine, logic evaluator, and testability technologies.
Atrenta has over forty-five customers, such as Agere, Agilent, Apple, ARM,
Canon, Compaq, Fujitsu, Hitachi, LSI Logic, Motorola, National Semiconductor,
NCR, Nortel and Olympus, who are using SpyGlass to achieve shorter overall
design cycles, increased design productivity and lower costs. Atrenta is
headquartered in San Jose, California, with European headquarters in Swindon,
England, a research and development center in India, and sales and support
distributors in Japan, Taiwan, India and Singapore. For further information,
visit the Atrenta website at www.atrenta.com
or call 1-866 ATRENTA.
Related Semiconductor IP
- 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
- 1.8V/3.3V I/O Library with ODIO and 5V HPD in TSMC 12nm
- 1.8V to 5V GPIO, 1.8V to 5V Analog in TSMC 180nm BCD
- 1.8V/3.3V GPIO Library with HDMI, Aanlog & LVDS Cells in TSMC 22nm
- Specialed 20V Analog I/O in TSMC 55nm
Related News
- Atrenta and Xilinx Partner to Deliver Predictive Analysis for Virtex Platform FPGAs
- Atrenta, the Predictive Analysis Company, adds new distributos worldwide
- Atrenta Introduces First Low-Power RTL Predictive Analysis Capability
- Atrenta Leverages Web to Enable Strategic Partners to Deliver Customized Predictive Analysis
Latest News
- Will RISC-V reduce auto MCU’s future risk?
- Frontgrade Gaisler Launches New GRAIN Line and Wins SNSA Contract to Commercialize First Energy-Efficient Neuromorphic AI for Space Applications
- Continuous-Variable Quantum Key Distribution (CV-QKD) system demonstration
- Latest intoPIX JPEG XS Codec Powers FOR-A’s FA-1616 for Efficient IP Production at NAB 2025
- VeriSilicon Launches ISP9000: The Next-Generation AI-Embedded ISP for Intelligent Vision Applications