Arteris Ncore Cache Coherent Interconnect IP Enabled by ARM's Cycle Models
Cycle-accurate SystemC models power highly scalable verification and performance optimization infrastructure
CAMPBELL, Calif -- May 25, 2016 -- Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced that it has used ARM® Cycle Models for use in hardware and performance verification of its Ncore Cache Coherent Interconnect IP.
Arteris has been a long-time partner with the Cycle Model team at ARM, with many mutual customers, and licensed ARM processor Cycle Models, Performance Analysis Kits and SoC Designer Plus for its own development use in 2014. The ARM Cycle Models provide fast, 100 percent cycle accurate simulation of the latest ARM processor IP, enabling the Arteris team to create a highly scalable infrastructure to verify compliance with the ARM AMBA® ACE protocol and to optimize the Ncore interconnect IP for a broad range of system-level use cases. The SoC Designer Plus Swap & Play technology was instrumental in the creation of fast virtual platforms running software test suites to characterize system bandwidth and latency for a multitude of use cases.
“ARM Cycle Models provide early, secure access to ARM’s leading edge IP,” said Javier Orensanz, general manager, development solutions group, ARM. “Enabling Arteris to integrate this technology into their development infrastructure highlights ARM’s commitment to enabling design optimization, time-to-market and cost-efficiency gains for our ecosystem partners.”
“ARM’s system-level modeling and virtual prototyping technologies have been critical to development of our new Ncore cache coherent technology,” said K. Charles Janac, President and CEO of Arteris. “Being able to quickly integrate the latest ARM IP into our testing infrastructure and simulate it on a large scale has helped us increase the quality of our product and produce a world-class performance optimization and verification environment.”
About Arteris
Arteris, Inc. provides system-on-chip (SoC) interconnect IP and tools to accelerate SoC semiconductor assembly for a wide range of applications. Rapid semiconductor designer adoption by customers such as Samsung, Huawei / Hisilicon, Mobileye, Altera, and Texas Instruments has resulted in Arteris being the only semiconductor IP company to be ranked in the Inc. 500 and Deloitte Technology Fast 500 lists in 2012 and 2013. Customer results obtained by using the Arteris product line include lower power, higher performance, more efficient design reuse and faster SoC development, leading to lower development and production costs. More information can be found at http://www.arteris.com.
Related Semiconductor IP
- 1.8V/3.3V I/O library with ODIO and 5V HPD in TSMC 16nm
- 1.8V/3.3V I/O Library with ODIO and 5V HPD in TSMC 12nm
- 1.8V to 5V GPIO, 1.8V to 5V Analog in TSMC 180nm BCD
- 1.8V/3.3V GPIO Library with HDMI, Aanlog & LVDS Cells in TSMC 22nm
- Specialed 20V Analog I/O in TSMC 55nm
Related News
- Arteris IP Ncore Cache Coherent Interconnect Licensed by Bitmain for Sophon TPU Artificial Intelligence (AI) Chips
- Arteris Ncore Cache Coherent Interconnect IP Certified for ISO 26262 Automotive Functional Safety Standard
- Arteris Expands Ncore Cache Coherent Interconnect IP To Accelerate Leading-Edge Electronics Designs
- Silicon-Proven Arteris IP Ncore Cache Coherent Interconnect Implemented in Toshiba ISO 26262-Compliant ADAS Chip
Latest News
- Will RISC-V reduce auto MCU’s future risk?
- Frontgrade Gaisler Launches New GRAIN Line and Wins SNSA Contract to Commercialize First Energy-Efficient Neuromorphic AI for Space Applications
- Continuous-Variable Quantum Key Distribution (CV-QKD) system demonstration
- Latest intoPIX JPEG XS Codec Powers FOR-A’s FA-1616 for Efficient IP Production at NAB 2025
- VeriSilicon Launches ISP9000: The Next-Generation AI-Embedded ISP for Intelligent Vision Applications