8051 Core Executes up to 300 MIPS in Actel Axcelerator* FPGA

Multi-CPU, 8051 instruction-set-compatible parallel controller executes up to 300 MIPS in Actel Axcelerator FPGA and features concurrent real-time monitoring/debugging of all 9 CPUs via JTAG using direct or TCP/IP connection

PLANO, Texas, July 19, 2003 -- QuickCores announces that its hyper-scalable 8051 instruction-set-compatible parallel controller soft core is now available for evaluation and licensing.  Dubbed the Pro8051HYPERCORE, the Verilog soft-core is a multi-CPU hyper-scalable, 8-bit microcontroller array building block for 8051 instruction-set-compatible parallel controller applications.  When implemented in either an Actel ProASICPLUS or Axcelerator FPGA, up to nine 8051 “hyper-core” CPUs (arranged as one “Bull” 8051 CPU and up to eight “Target” 8051 CPUs) may be cascaded together to form an array of up to nine autonomous 8051 controllers that can be hyper-scaled (wholly or partially at the behest of the “Bull” 8051 CPU) and operated as a single, parallel controller unit.

Hyper-Scalable Architecture
To achieve hyper-scalability, the Pro8051HYPERCORE utilizes an instruction superset which is 100% 8051 machine and source code compatible with the industry standard 8051 instruction set and existing “C” compilers.   The Pro8051HYPERCORE is based on a patent-pending cascaded instruction pipeline architecture that allows the “Bull” 8051 CPU to use its own native hyper-scale instructions to command specific target 8051 CPU(s) to perform a specific task, or to access and manipulate any program or data memory location, or any special function register (SFR), of any target CPU under it, as if it were the Bull CPU’s own resource, in real-time, even while the target(s) are running their own application or halted at a breakpoint.

Part of the Pro8051HYPERCORE instruction repertoire includes special hyper-scale instructions that are fetched by the “Bull” 8051 CPU and decoded and executed by the “Target” 8051 CPU(s) specified in the hyper-scale instructions.  This allows from one to eight Target 8051 CPUs to execute instructions in parallel, or initiate execution of “bit-banging” sequences simultaneously.  The architecture’s cascaded instruction pipeline gives priority to the “Bull” CPU’s hyper-scale instructions such that even while the responsive Target 8051 CPU(s) are fetching and executing their own instructions from their own local program memory, they will complete the execution of greater priority hyper-instructions (originally fetched and decoded by the “Bull” CPU from the Bull’s program memory) and then resume execution of their own “local” instructions where they left off.  

Hardware Real-Time Monitor
Each of the hyper-core’s 8051 CPUs is built on an enhanced version of QuickCores real-time monitor architecture that allows the CPUs to be monitored and debugged concurrently in real-time using a single QuickCores JTAG controller pod.  Since the real-time monitor is in hardware, no monitor program software is required anywhere on the target side of the Pro8051HYPERCORE.  The real-time monitor architecture allows applications developers to remotely examine and edit any program, data, or SFR location of the “Bull” 8051, or any “Target” 8051, “on-the-fly” without first having to halt the microcontroller.  This capability is invaluable for developing real-time applications such as motor control and instrumentation where halting the CPU in order to change a operational parameter or coefficient could be catastrophic to the application hardware.

Development Tools
The Pro8051HYPERCORE is supported by Keil Software 8051 “C” compiler and Domain Technologies BoxView* “C” source-level debugger.  An entry-level evaluation/development kit featuring a “Dual CPU” version of the Pro8051HYPERCORE implemented in a Actel ProASICPLUS (APA-150 in a TQFP-100 pin package) is available for $499.  The entry-level kit comes with QuickCores QuickFLASH-USB+ JTAG APA device programming/debug pod and BoxView C source level debugger.  

The entry-level development board features 32-kbytes of non-volatile program/data RAM, 2x16 character LCD, and a 96-pin connector which mates with the 96-pin connector found on Cygnal* Integrated Products (“Cygnal”) C8051F12x, C8051F02x, C8051F04x, C8051F06x development boards.  Developers can use the Cygnal CPU as the “Bull” to create their own hyper-scalable 8051 hybrid multi-CPU parallel controller and monitor and debug in real time both boards using the same QuickCores JTAG controller pod and connector. The entry level board can of course be used as a stand-alone Dual-8051, hyper-scalable parallel controller.

A professional developer’s kit that features a 9-CPU Pro8051HYPERCORE implemented in an Axcelerator AX2000 FPGA (in a FG896 package) is also available for $3,000.  Lead-time is eight weeks.

About QuickCores
QuickCores develops and licenses synthesizable microcontroller IP for embedding in FPGA and ASIC devices.  Since its inception in 1996, QuickCores has been focused on adapting the models of popular microcontrollers to include on-chip, real-time monitoring and debug capability.  All of QuickCores 8051, 6805 and 16C5x microcontroller IP is built on a patented real-time monitor and data exchange architecture that enables high speed exchange and monitoring of data between target and host using a JTAG interface.  For more information about QuickCores and its products, visit www.quickcores.com  .

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* ProASICPLUS and Axcelerator are a trademarks of Actel Corporation.  Pro8051, Pro8051+, and Pro8051HYPERCORE are trademarks of QuickCores IP.  Cygnal is a trademark of Cygnal Integrated Products, Inc.