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Compare 242 IP from 59 vendors (1 - 10)
  • Multi-core capable 64-bit RISC-V CPU with vector extensions
    • The SiFive® Intelligence™ X180 core IP products are designed to meet the increasing requirements of embedded IoT and AI at the far edge.
    • With this 64-bit version, X100 series IP delivers higher performance and better integration with larger memory systems.
    Block Diagram -- Multi-core capable 64-bit RISC-V CPU with vector extensions
  • Multi-core capable 32-bit RISC-V CPU with vector extensions
    • The SiFive® Intelligence™ X160 core IP products are designed to meet the increasing requirements of embedded IoT and AI at the far edge.
    • With this 32-bit version, X100 series IP can be optimized for power efficiency and severely area-constrained applications.
    Block Diagram -- Multi-core capable 32-bit RISC-V CPU with vector extensions
  • Multi-core capable RISC-V processor with vector extensions
    • The SiFive® Intelligence™ X280 Gen 2 is an 8-stage dual issue, in-order, superscalar design with wide vector processing (512 bit VLEN/256-bit DLEN).
    • It supports RISC-V Vectors v1.0 (RVV 1.0) and SiFive Intelligence Extensions to accelerate critical AI/ML operations.
    Block Diagram -- Multi-core capable RISC-V processor with vector extensions
  • Ultra-low power consumption out-of-order commercial-grade 64-bit RISC-V CPU IP
    • Dubhe-70 is a 9+ stage, 3-issue, out-of-order CPU IP that supports the rich RISC-V instruction set, RV64GCBH_Zicond_Zicbom_Zicboz_Zicbop.
    • With a score of 7.2 SPECInt2006/GHz, Dubhe-70 targets applications that require highly energy-efficient computation, including mobile, desktop, AI, and automotive.
    Block Diagram -- Ultra-low power consumption out-of-order commercial-grade 64-bit RISC-V CPU IP
  • High Performance 64-bit RISC-V Processor
    • Dubhe-90 is a high-performance commercial RISC-V CPU Core IP that is deliverable.
    • It adopts an 11+ stage and 5-issue pipeline, superscalar, and deep out-of-order execution, and supports standard RISC-V RV64GCBH extensions.
    Block Diagram -- High Performance 64-bit RISC-V Processor
  • Custom RISC-V Processor
    • Traditional processors no longer strike the right balance between high performance, energy consumption, and cost.
    • Keysom processors deliver powerful capabilities, optimizing IoT and AI workflows with energy-efficient, small-footprint solutions.
    Block Diagram -- Custom RISC-V Processor
  • RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
    • Built on RISC-V and delivered as soft chiplet IP, the Veyron E2X provides scalable, standards-based AI acceleration that customers can integrate and customize freely.
    Block Diagram -- RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
  • Scalable RISC-V CPUs for Data Center, Automotive, and Intelligent Edge
    • 11+ SPECint2017 (rate=1) at up to 4.2 GHz
    • Enhanced RISC-V standard matrix extension support alongside RVV 1.0 and scalar compute
    • 24 TeraFLOPS/core of FP8 matrix compute for AI/ML acceleration, or up to 4.5 PFLOPS in a 192-core chiplet-based SiP
    • Significantly higher IPC and performance-per-watt, driven by new microarchitecture innovations
  • 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
    • 2 different packages with or without vector: AX46MPV, AX46MP
    • in-order dual-issue 8-stage CPU core with up to 2048-bit VLEN
    • Symmetric multiprocessing up to 16 cores
    • Private Level-2 cache
    • Shared L3 cache and coherence support
    Block Diagram -- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
  • 32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM
    • AndesCore™ A46MP(V) 32-bit multicore CPU IP is an 8-stage superscalar processor with Vector Processing Unit (VPU) based on AndeStar™ V5 architecture and Andes Matrix Multiply (AMM) extension.
    • It supports RISC-V standard “G (IMA-FD)”, “ZC” compression, “B” bit manipulation, DSP/SIMD ‘P’ (draft), “V” (vector), CMO (cache management) extensions, Andes performance enhancements, plus Andes Custom Extension™ (ACE) for user-defined instructions.
    Block Diagram -- 32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM
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