D2D IP
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19
IP
from 10 vendors
(1
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10)
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UCIe PHY & D2D Adapter
- 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
- UCIe v1.1 specification
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UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
- Emerging Standard Knowledge
- Flexibly Configurable
- Best in Class PPA
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D2D UCIe
- Compatible with UCIe v1.1 specification
- Features single-ended, source-synchronous, and DDR I/O signaling
- Supports 32-bit (16-bits TX + 16-bit RX) data bus per module for standard packages
- Offers a high clock frequency up to 16GHz
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40G Ultralink D2D PHY for TSMC 7nm
- Flexible data rate from 20Gbps to 40Gbps
- Single-ended NRZ signaling scheme
- BIST features ensure Known Good Die (KGD)
- Sideband for link management
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40G Ultralink D2D PHY for TSMC 5nm
- Flexible data rate from 20Gbps to 40Gbps
- Single-ended NRZ signaling scheme
- BIST features ensure Known Good Die (KGD)
- Sideband for link management
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40G Ultralink D2D PHY for Samsung 7LPP
- Flexible data rate from 20Gbps to 40Gbps
- Single-ended NRZ signaling scheme
- BIST features ensure Known Good Die (KGD)
- Sideband for link management
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40G Ultralink D2D PHY for GF12LP+
- Flexible data rate from 20Gbps to 40Gbps
- Single-ended NRZ signaling scheme
- BIST features ensure Known Good Die (KGD)
- Sideband for link management
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40G Ultralink D2D PHY for TSMC 3nm
- Flexible data rate from 20Gbps to 40Gbps
- Single-ended NRZ signaling scheme
- BIST features ensure Known Good Die (KGD)
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Die-to-Die (D2D) Interconnect
- Adaptable to any communication protocols including extending SkyeChip’s Non-Coherent and Coherent NOC interconnects across multiple dies
- Architected to significantly reduce wiring overhead across multiple dies
- Supports transfer rates of up to 6.4GT/s
- Supports major 2.5D and 3D inter-die packaging technologies
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2GBps Low Power D2D Interface
- Core Device: 0.9V
- I/O Device: 1.8V Standard
- Core: Uses SVT only