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Search (24)
Compare 24 IP from 15 vendors (1 - 10)
  • UCIe D2D Adapter
    • The D2D Adapter for UCIe is a scalable adapter layer between one or more protocol components and the UCIe PHY, which ensures efficient data transfer across the UCIe Link by seamlessly coordinating with the Protocol Layer and Physical Layer.
    • By minimizing logic on the main data path, it delivers a low-latency, optimized pathway for protocol Flits.
    Block Diagram -- UCIe D2D Adapter
  • D2D UCIe 1.1
    • Compatible with UCIe v1.1 specification
    • Features single-ended, source-synchronous, and DDR I/O signaling
    • Supports 32-bit (16-bits TX + 16-bit RX) data bus per module for standard packages
    • Offers a high clock frequency up to 16GHz
    Block Diagram -- D2D UCIe 1.1
  • D2D UCIe 1.0
    • Compatible with UCIe v1.0 specification
    • Single-ended, source synchronous and DDR IO Signaling
    • Supports 32 bits(16bits TX + 16bits RX) data bus per module for standard package
    • High clock frequency, up to 8GHz
    Block Diagram -- D2D UCIe 1.0
  • UCIe PHY & D2D Adapter
    • 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
    • UCIe v1.1 specification
    Block Diagram -- UCIe PHY & D2D Adapter
  • 40G UltraLink D2D PHY
    • Innovative mixed-signal architecture to achieve high bandwidth, ultra low latency and low power 
    • Flexible data rate from 20Gbps to 40Gbps 
    • Built-in self-test features to ensure “known good die” 
    • Interoperable between different technology nodes and foundries 
    • Easy routing and straightforward integration 
    • Achieves better than 10-15 bit error rate (BER) without requiring forward error correction (FEC) 
    • Integrated scrambling and lane de-skew functionality 
    • Supports -40ºC to 125ºC industrial temperature range 
    Block Diagram -- 40G UltraLink D2D PHY
  • D2D Controller addon for D2D SR112G PHY with CXS interface
    • Low Latency controller for die-to-die connectivity
    • Supports PAM-4 and NRZ PHY signaling mode in all data rates
    • Reduces BER with optional FEC configurations
    • Supports Arm® AMBA® CXS interface
    Block Diagram -- D2D Controller addon for D2D SR112G PHY with CXS interface
  • 2Gbps Low Power D2D Interface
    • Core Device: 0.8V
    • I/O Device: 1.8V Standard
    • Core: Uses SVT only
    • BEOL: M8 and below
  • Low Power D2D Interface in TSMC 16nm FFC/FFC+
    • This library is a production-quality, silicon-proven custom Die-to-Die high speed interface available in TSMC’s 16nm process.
    • The I/O cell is bidirectional, has two modes of operation: standard full rail to rail swing, or a custom low noise pseudo-differential interface.
    • The RX cells have a weak pull-down feature.
    Block Diagram -- Low Power D2D Interface in TSMC 16nm FFC/FFC+
  • Verification IP for UCIe
    • Avery UCIe VIP provides a comprehensive verification solution featuring an advanced UVM environment that incorporates constrained random traffic gener ation, robust D2D and LogPHY layer controls and error injection, protocol checks and coverage, functional coverage, protocol analyzer-like features for debug ging, and performance analysis metrics.
    • PCIe/CXL VIP supports FDI/RDI adapters for complete stack verification. With the advanced capabilities of Avery VIP, engineers can work more efficiently, develop more complex tests, and work on more complex topologies, such as bifurcation.
    Block Diagram -- Verification IP for UCIe
  • UCIe Chiplet PHY & Controller
    • Compliant with the UCIe specification (2.0 & 1.1)
    • Flexible Structure, easy to customize (Pre-hardened PHY tuned to Customer Spec, PHY + Adapter Layer, PHY + Adapter Layer + Customized Protocol Layer)
    • Supports the CXS/AXI using the streaming package (AXI Interface bandwidth up to 89%)
    Block Diagram -- UCIe Chiplet PHY & Controller
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