IP Catalog > Parallel FFT

parallel FFT IP

Filter
Filter

Login required.

Sign in

Search (10)
Compare 10 IP from 6 vendors (1 - 10)
  • Dual Parallel FFT
    • Fastest most power efficient architecture optimized for 128 to 4096 points FFTs
    • Optimized Butterflies/Dragonflies, reductions from constant twiddle factors reduces logic
    • No pipeline limit, fully asynchronous to maximum pipeline stages
    • upto 32 points in/out per clock cycle, ultra high performance, 12.5 GSPS+ possible in FPGA
  • Parallel FFT
    • Fastest most power efficient architecture optimized for short FFTs, 4 to 64 points
    • Optimized Butterflies/Dragonflies, reductions from constant twiddle factors reduces logic
    • No pipeline limit, fully asynchronous to maximum pipeline stages
    • N points in/out per clock cycle, ultra high performance, 25 GSPS+ possible in FPGA
  • Parallel Butterfly FFT
    • ParaCore Architect parametric-based core provides maximum adaptability and flexibility (see details on the FFT Parameters)
    • Completely proven in many real-world applications
    • Supports any radix-2 length FFT and IFFT transformations
    • Variable length option for runtime per-transform length select
  • ASIP-1 FFT Engine
    • Platform to design Application Specific Instruction Set Processors (ASIPs).
    • Ideal for supporting multi-standard systems.
    • Supports a wide range of complex DSP functions.
    Block Diagram -- ASIP-1 FFT Engine
  • Mixed Radix FFT
    • lengths other than radix-2 possible (i.e. 768, 256 x 3)
    • Parallel FFT structures to increase performance
    • Fixed or floating point math
    • wide range of performance options
  • 128-Point FFT/IFFT IP Core
    • The FFT4T core implements a 128 point complex FFT and IFFT over 12 data streams in hardware. It runs at the clock frequency four times higher than the insput sampling frequency.
    • FFT4T core is a specialized FFT/IFFT processor intended for a situation where an RF signal is recieved over multiple channels in parallel and its filtering is to be performed in the frequency domain. The core fits nicely into, for example, a multichannel GPS system.
    Block Diagram -- 128-Point FFT/IFFT IP Core
  • Ultra High Speed FFT/IFFT processor
    • Highly pre-synthesis design configurability with detailed generic/parameter values, in order to meet desired implementation trade-offs.
  • DVB-T2 Demodulator and LDPC/ BCH Decoder
    • DVB-T2 EN302 755 V1.2.1, Rev.9 compliant  
    • Supports IF input  
    • Single input – Single output (SISO)  
    • Sampling frequency offset (SFO) tracking and compensation  
    • Carrier frequency offset (CFO) detection and correction  
  • ASIP-2 Programmable Filter Engine
    • Platform to design Application Specific Instruction Set Processors (ASIPs).
    • Ideal for supporting multi-standard systems.
    • Supports a wide range of complex DSP functions
    • The ASIP2 performs Fast Fourier Transform (FFT) to convert time domain signals to frequency domain signals for further processing. It supports FFT sizes from 4 to 8K.
    Block Diagram -- ASIP-2 Programmable Filter Engine
  • DVB-S2X Multi-Carrier Demodulator
    • Supports CCM, ACM and VCM
    • Supports roll-off factors 5%, 10%, 15%, 20%, 25% to 35%
    • Support for short and normal blocks (16,200 bits and 64,800 bits) with pilots only
    • Support for QPSK to 256-APSK
    Block Diagram -- DVB-S2X Multi-Carrier Demodulator
×
Semiconductor IP