ASIP-1
Overview
The programmable filter engine (PFE) is a configurable and expandable IP that implements FIR, decimation, interpolation and IIR filtering functions. The user is afforded the ability to allocate and configure the resources of a set of instantiated filtering element functions to satisfy the project requirements. A micro-code program is developed, using the engine's instruction set, to configure the connectivity of the engine filter elements and then to control the engine execution of the required filtering functions.
Key Features
- Platform to design Application Specific Instruction Set Processors (ASIPs).
- Ideal for supporting multi-standard systems.
- Supports a wide range of complex DSP functions .
- The ASIP1 supports the implementation of multiple DSP functions such as Kalman filtering suitable for IQ mismatch.and Finite and Infinite Impulse Response filtering with higher filter order.
- Also supports IQ mismatch estimation and correction techniques for OFDM systems such as Transmit IQ (TxIQ) Estimation, Transmit IQ (TxIQ) Compensation, Receive IQ (RxIQ) Estimation and Receive IQ (RxIQ) Compensation.
- Ported C compiler, assembler, linker, and debugger suitable for the sample target.
- The ASIP1 targets pack up to six independent operations to be executed in parallel in one instruction word of 32~bits
- Ability to easily target other signal processing applications.
Benefits
- Flexibiltiy to allocate and re-allocate resources among filtering requirements
- On-the-fly modification of filter characteristics
- Sharing of filtering resources among multiple functions
- Optimized method to implement symmetric and non-symmetric FIRs
- Ability to execute multiple micro-code programs under user control
- Execution of multiple nested loops
Block Diagram
Applications
- Wired/Wireless MODEMs (DSL, LTE, Zigbee, ...)
- Image processing
- Speech recognition/Speech synthesis
- Filters, decimators, and interpolators
Deliverables
- Synthesizable Verilog
- System Model (Matlab or C code) and documentation
- Microcode assembler
- Verilog Test Benches
- Documentation
Technical Specifications
Maturity
Mature
Availability
Now