Z80 IP

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Compare 7 IP from 3 vendors (1 - 7)

Advanced 8-bit microprocessor
- Fully compatible with Z80 industry standard
- Fully synthesizable, static synchronous de-sign with no internal tri-states
- No internal reset generator or gated clock
- Scan test ready
Rabbit (TM) 2000 microprocessor
- 8/16 bit CPU, four serial ports, five parallel ports, timers, real-time clock, and low-EMI features.
High-performance implementation of Z80/Z180 instruction set
- Full Z80/Z180 instruction set. Separate memory and I/O buses,
- optimized for direct connection to standard ASIC or FPGA
- memories and industry-standard peripheral functions. Separate
- interrupt vector bus for use with an optionaql external interrupt
Clean-room clone of Zilog Z8002 CPU
- Regular CISC architecture, with 16 general-purpose registers. 16-bit program counter. Includes 16x16 and 32x32 multiply as well as 64/32 and 32/16 divide.
Exact Copy of the Z80-SIO
- Technology-independent Verilog HDL implementation.
- 8-bit CPU interface.
- Two independent full-duplex channels.
- Receivers are quadruply buffered; transnmitters are doubly-buffered.
Local Area Network Controller
- Compatible with Ethernet and IEEE 802.3 10BASE 5 Type A, and 10BASE 2 Type B, 10BASE-T
- Easily interfaced with 80x86, 680x0, Am29000?, Z8000TM, LSI-IITM microprocessors.
- Can be programmed by the host using its internal control and status registers.
- Supports 16 bit wide multiplexed data bus and 24 bit wide address bus.
Clean-room clone of Z180 TM CPU
- Fully functional synthesizable Verilog HDL model of the Z80180 TM CPU
- Vendor and technology independent
- Software compatible with several industry-standard processors
- 181 Instructions, plus an undefined opcode trap