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USB 3.2 IP

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Compare 208 IP from 26 vendors (1 - 10)
  • USB 3.2 Dual Role Device (DRD) Controller
    • USB 3.2 Dual Role Device (DRD) softcore semiconductor IP is designed for applications requiring both USB Host and Device implementation.
    • This core comprises USB3.2 SSP, SS, HS/FS/LS Host, and Device controllers in a single codebase that supports role-swap functionality
  • USB 3.2 - Validates high-speed USB designs for protocol compliance and performance
    • XtremeSilica’s USB 3.2 Verification IP offers a comprehensive solution for validating designs based on the USB 3.2 specification. It supports SuperSpeed+ data rates up to 20 Gbps, ensuring protocol compliance, power management, and seamless interoperability across versions.
    • The product’s advanced features include dynamic link negotiation validation, error injection, and robust debugging tools. It enables testing across a range of devices, ensuring high-speed data transfer and reliable performance in both legacy and modern USB designs
    Block Diagram -- USB 3.2 - Validates high-speed USB designs for protocol compliance and performance
  • USB 3.2 Verification IP
    • Fully compliant with USB 3.2 specification version 1.1, xHCI Specification Revision 1.2, and Pipe Interface 6.1.1 with Message Bus Interface for USB3.2 Architecture with backward compatibility to USB3.1, USB3.0 and USB2.0 (including USB2.0, USB 3.0. OTG)
    • Supports USB Type-C.
    • Supports up to 128 devices including hub and device on any tier level.
    • Supports 15 IN and 15 OUT and 1 control endpoint for each device.
    Block Diagram -- USB 3.2 Verification IP
  • USB 3.2 Device Controller
    • USB Device Controller with protocol-layer and link-layers implementation
    • USB3 Gen2 x2 link with fallback to Gen2 x1, Gen1 x2, Gen1 x1, and backward compatibility for USB2 High/Full Speed modes
    Block Diagram -- USB 3.2 Device Controller
  • USB 3.2 ReTimer
    • USB 3.2 Retimer softcore is designed for use in USB Port/Cable Retimer applications with USB SuperSpeed Plus/SuperSpeed link operations.
    • The IP has been verified in simulation and is synthesis clean for FPGA implementations
    Block Diagram -- USB 3.2 ReTimer
  • USB 3.2 Host Controller
    • USB3 Gen2 x2 link with fallback to Gen2 x1, Gen1 x2, Gen1 x1, and backward compatibility for USB2 High/Full/Low Speed modes. Support PIPE and UTMI+/ULPI interfaces with full link power management.
    • The clock domain crossing mechanism between USB and xHCI/system-bus logic provides flexibility for easy integration. 
    Block Diagram -- USB 3.2 Host Controller
  • USB 3.2 Gen2x2 with PIPE 4.3 and USB2.0 with UTMI+ interface
    • Fully compliant with USB 3.2 Gen2x1 featuring PIPE 4.3 and USB 2.0 with a UTMI+ interface
    • Supports host, peripheral, and dual-role applications
    • Supports 10/12/25/30/19.2/24/27/40 MHz crystal oscillators or clock inputs
    • Supports TX 3-Tap FFE and RX CTLE+1-Tap DFE for SS+
    Block Diagram -- USB 3.2 Gen2x2 with PIPE 4.3 and USB2.0 with UTMI+ interface
  • USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 28HPC+
    • Worldwide smallest USB 3.2 Gen2X1 PHY IP in 12/16nm process (IP size is smaller than 0.46mm²)
    • Fully compliant with Universal Serial Bus (USB) 3.2 Gen2X1 and 2.0 electrical specifications
    • Supports clock inputs from 25MHz crystal oscillator and external clock sources from the core
    • Supports 3-Tap FIR Equalization for TX and CTLE+1-Tap DFE for RX
    Block Diagram -- USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 28HPC+
  • USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 16FFC
    • Worldwide smallest USB 3.2 Gen2X1 PHY IP in 12/16nm process (IP size is smaller than 0.46mm²)
    • Fully compliant with Universal Serial Bus (USB) 3.2 Gen2X1 and 2.0 electrical specifications
    • Supports clock inputs from 25MHz crystal oscillator and external clock sources from the core
    • Supports 3-Tap FIR Equalization for TX and CTLE+1-Tap DFE for RX
    Block Diagram -- USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 16FFC
  • USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 12FFC
    • Worldwide smallest USB 3.2 Gen2X1 PHY IP in 12/16nm process (IP size is smaller than 0.46mm²)
    • Fully compliant with Universal Serial Bus (USB) 3.2 Gen2X1 and 2.0 electrical specifications
    • Supports clock inputs from 25MHz crystal oscillator and external clock sources from the core
    • Supports 3-Tap FIR Equalization for TX and CTLE+1-Tap DFE for RX
    Block Diagram -- USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 12FFC
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