USB 3.2 IP
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194
IP
from 25 vendors
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10)
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Super-Speed Plus USB 3.2 Hub Controller
- Supports two lanes or one lane - easily configurable
- Number of downstream ports can be easily selected
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USB 3.2 Gen2x2 with PIPE 4.3 and USB2.0 with UTMI+ interface
- Fully compliant USB 3.2 Gen2x2 with PIPE 4.3 and USB2.0 with UTMI+ interface
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USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 28HPC+
- Worldwide smallest USB 3.2 Gen2X1 PHY IP in 12/16nm process (IP size is smaller than 0.46mm²)
- Fully compliant with Universal Serial Bus (USB) 3.2 Gen2X1 and 2.0 electrical specifications
- Supports clock inputs from 25MHz crystal oscillator and external clock sources from the core
- Supports 3-Tap FIR Equalization for TX and CTLE+1-Tap DFE for RX
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USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 16FFC
- Worldwide smallest USB 3.2 Gen2X1 PHY IP in 12/16nm process (IP size is smaller than 0.46mm²)
- Fully compliant with Universal Serial Bus (USB) 3.2 Gen2X1 and 2.0 electrical specifications
- Supports clock inputs from 25MHz crystal oscillator and external clock sources from the core
- Supports 3-Tap FIR Equalization for TX and CTLE+1-Tap DFE for RX
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USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 12FFC
- Worldwide smallest USB 3.2 Gen2X1 PHY IP in 12/16nm process (IP size is smaller than 0.46mm²)
- Fully compliant with Universal Serial Bus (USB) 3.2 Gen2X1 and 2.0 electrical specifications
- Supports clock inputs from 25MHz crystal oscillator and external clock sources from the core
- Supports 3-Tap FIR Equalization for TX and CTLE+1-Tap DFE for RX
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USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 7FF
- Worldwide smallest USB 3.2 Gen2X1 PHY IP in 12/16nm process (IP size is smaller than 0.46mm²)
- Fully compliant with Universal Serial Bus (USB) 3.2 Gen2X1 and 2.0 electrical specifications
- Supports clock inputs from 25MHz crystal oscillator and external clock sources from the core
- Supports 3-Tap FIR Equalization for TX and CTLE+1-Tap DFE for RX
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USB 3.2/ PCIe 3.1/ SATA 3.2 Combo PHY IP, Silicon Proven in UMC 28HPC
- Compliant with PCIe 3.1 Base Specification
- Compliant with Universal Serial Bus 3.2 Specification
- Compliant with Universal Serial Bus 2.0 Specification
- Compliant with UTMI 1.05 Specification
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USB 3.2 Controller IP
- Lowest risk: Based on proven USB 3.2 controller shipped in millions of units
- Lowest power: Extend battery life in mobile devices (USB power saving modes, Uniform Power Format, hibernation option with dual power rails)
- Configurable data buffering options to optimize performance vs area
- Supports all USB speed modes
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USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm,6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
- USB 3.2 Gen2
- 1. Worldwide smallest USB 3.2 Gen2 PHY IP (e.g. IP size @28HPC+ is smaller than 0.7mm²)
- 2. Fully compliant with Universal Serial Bus (USB) 3.2 Gen2 and 2.0 electrical specifications
- 3. Supports clock inputs from 10/12/19.2/24/25/27/30/40MHz crystal oscillator and external clock sources from the core
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USB 3.2 Gen2 PHY IP, Silicon Proven in UMC 28HPC
- Worldwide smallest USB 3.2 Gen2X1 PHY IP in 12/16nm process (IP size is smaller than 0.46mm²)
- Fully compliant with Universal Serial Bus (USB) 3.2 Gen2X1 and 2.0 electrical specifications
- Supports clock inputs from 25MHz crystal oscillator and external clock sources from the core
- Supports 3-Tap FIR Equalization for TX and CTLE+1-Tap DFE for RX