USB3 Gen2 x2 link with fallback to Gen2 x1, Gen1 x2, Gen1 x1, and backward compatibility for USB2 High/Full/Low Speed modes. Support PIPE and UTMI+/ULPI interfaces with full link power management. The clock domain crossing mechanism between USB and xHCI/system-bus logic provides flexibility for easy integration.
USB 3.2 Host Controller
Overview
Key Features
- AMBA-AXI system-bus interface for configuration-space access and data-path interface
- Bulk-stream for USB Attached SCSI Protocol (UASP) transfers
- Up to 16 IN and OUT Endpoints including control Endpoint
- Sideband interrupt and message signal interrupts
- Precision Time Measurement (PTM)
Block Diagram
Technical Specifications
Maturity
Available on Request
Availability
Available on Request