USB3.2 Retimer Controller
Overview
MosChip USB3.2 Retimer softcore is designed for use USB Port/Cable Retimer applications with USB SuperSpeedPlus/SuperSpeed link operations The IP has been verified in simulation and is synthesis clean for FPGA implementations. The core is highly power efficient for port or cable retimer applications
Key Features
- Spec reference:
- Intel PIPE v4.3
- SuperSpeedPlus @10Gbps with fallback to SuperSpeed @5Gbps
- USB-Link parallel data-path 20bit for SS, and 32bit for SSP
- Implements Digital-PHY PCS as part of the core supporting 8b/10b and 128b/132b codec with scrambler and descrambler, error detection-correction, Clock offset compensation with elasticity buffer, LFPS, full LPM, and compliance-mode"
Block Diagram
Technical Specifications
Maturity
Available on Request
Availability
Available on Request
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- Single Wire Protocol (SWP) slave digital controller compliant with the ETSI 102.613 standard