USB 3.2 Gen2 PHY IP, Silicon Proven in TSMC 28HPC+
Overview
All USB 3.2 Gen2X1 host and peripheral applications up to 10Gbps are supported by the USB 3.2 Gen2X1 transceiver IP. It complies with UTMI+ and PIPE4.0 requirements. The USB 3.2 Gen2X1 IP is backward compatible with high-speed data rates of 480Mbps, full-speed data rates of 12Mbps, and low-speed data rates of 1.5Mbps and has high-speed mixed signal circuits to accommodate Gen2 and Gen1 traffic. In order to support the USB Type-C connector, the USB 3.2 Gen2X1 IP offers an active switch to enable bi-directional plug-in and specific functionality (such as VBUS setup and USB attachment cable orientation recognition) through the CC1/CC2 pins defined in the Type-C connection.
Key Features
- Worldwide smallest USB 3.2 Gen2X1 PHY IP in 12/16nm process (IP size is smaller than 0.46mm²)
- Fully compliant with Universal Serial Bus (USB) 3.2 Gen2X1 and 2.0 electrical specifications
- Supports clock inputs from 25MHz crystal oscillator and external clock sources from the core
- Supports 3-Tap FIR Equalization for TX and CTLE+1-Tap DFE for RX
- Integrates an active switch to support the orientation-less connection with USB Type-C connector
- Provides an auxiliary CC module IP to support USB Type-C related functions
- Supports both wire-bond and flip-chip package type
- Silicon Proven in TSMC 28HPC+
Block Diagram
Deliverables
- GDSII & layer map
- Place-Route views (.LEF)
- Liberty library (.lib)
- Verilog behaviour model
- Netlist & SDF timing
- Layout guidelines, application notes
- LVS/DRC verification reports
Technical Specifications
Maturity
In Production
Availability
Immediate
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