UCIe PHY IP

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Compare 58 IP from 17 vendors (1 - 10)
  • UCIe PHY (Die-to-Die) IP
    • Compliant with UCIe v2.0, supporting 4/8/12/16/24/32GT/s data rates
    • for Standard Package up to 16 lanes / for Advanced Package up to 64 lanes
    • Provides a 1024-bit data bus width with high-throughput die-to-die communication
    • Includes automatic per-lane calibration and optional transmitter de-emphasis
    Block Diagram -- UCIe PHY (Die-to-Die) IP
  • UCIe PHY & D2D Adapter
    • 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
    • UCIe v1.1 specification
    Block Diagram -- UCIe PHY & D2D Adapter
  • UCIe PHY & Controller
    • Lightweight die-to-die interconnect solution consisting of the Physical Layer, Die-to-Die Layer and Protocol Layer optimized for highest performance with the lowest power and area overhead that is compliant to the Universal Chiplet Interconnect Express (UCIe) 2.0 specification.
  • UCIe Chiplet PHY & Controller
    • Compliant with the UCIe specification (2.0 & 1.1)
    • Flexible Structure, easy to customize (Pre-hardened PHY tuned to Customer Spec, PHY + Adapter Layer, PHY + Adapter Layer + Customized Protocol Layer)
    • Supports the CXS/AXI using the streaming package (AXI Interface bandwidth up to 89%)
    Block Diagram -- UCIe Chiplet PHY & Controller
  • UCIe and BOW Universal PHY
    • Novel Redundancy for Hi-Rel,
    • Support for 16&18-bit wide data,
    • Support Synchronous Operation,
    • Supports Advanced packaging,
    Block Diagram -- UCIe and BOW Universal PHY
  • UCIe IP
    • Supporting x16 link width with speeds up to 16 GT/s per lane, it conforms to UCIe’s standardized interface for seamless chiplet integration.
    • Developed on GlobalFoundries 12LP+, this IP includes custom PHY, protocol, and die-to-die layers—engineered for performance, flexibility, and low latency.
  • TSMC CLN5FF GUCIe LP Die-to-Die PHY
    • IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face advanced package.
    • This GUCIe PHY not only supports UCIe specification rev 1.1 compliance physical layer and Raw D2D interface (RDI) but also optionally provides the
    Block Diagram -- TSMC CLN5FF GUCIe LP Die-to-Die PHY
  • UCIe Controller add-on CXL2 Protocol Layer

     

    • UCIe Controller add-on CXL2 Protocol Layer
    Block Diagram -- UCIe Controller add-on CXL2 Protocol Layer
  • UCIe Controller add-on CXL3 Protocol Layer
    • UCIe Controller add-on CXL3 Protocol Layer
    Block Diagram -- UCIe Controller add-on CXL3 Protocol Layer
  • UCIe Controller baseline for Streaming Protocols for ASIL B Compliant, AEC-Q100 Grade 2
    • UCIe Controller baseline for Streaming Protocols for ASIL B Compliant, AEC-Q100 Grade 2
    • Low latency controller for UCIe-based multi-die designs
    • Includes Die-to-Die Adapter layer and Protocol layer
    Block Diagram -- UCIe Controller baseline for Streaming Protocols for ASIL B Compliant, AEC-Q100 Grade 2
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